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- research-articleMarch 2024
Reduced On-chip Storage of Seeds for Built-in Test Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 3Article No.: 45, Pages 1–16https://doi.org/10.1145/3643810Logic built-in self-test (LBIST) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-based LBIST ...
- research-articleMay 2018
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 4Article No.: 53, Pages 1–18https://doi.org/10.1145/3201405Close-to-functional scan-based tests are expected to create close-to-functional operation conditions in order to avoid overtesting of delay faults. Existing metrics for the proximity to functional operation conditions are based on the scan-in state. For ...
- research-articleJanuary 2017
Computation of Seeds for LFSR-Based n-Detection Test Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 2Article No.: 29, Pages 1–13https://doi.org/10.1145/2994144This article describes a new procedure that generates seeds for LFSR-based test generation when the goal is to produce an n-detection test set. The procedure does not use test cubes in order to avoid the situation where a seed does not exist for a given ...
- research-articleMay 2016
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 1Article No.: 7, Pages 1–22https://doi.org/10.1145/2911983This article describes a procedure for test data compression targeting functional and partially functional broadside tests. The scan-in state of such a test is either a reachable state or has a known Hamming distance from a reachable state. Reachable ...
- research-articleJune 2015
Design for low test pattern counts
- Haluk Konuk,
- Elham Moghaddam,
- Nilanjan Mukherjee,
- Janusz Rajski,
- Deepak Solanki,
- Jerzy Tyszer,
- Justyna Zawada
DAC '15: Proceedings of the 52nd Annual Design Automation ConferenceJune 2015, Article No.: 136, Pages 1–6https://doi.org/10.1145/2744769.2744817This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test ...
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- ArticleNovember 2014
A Case Study on Implementing Compressed DFT Architecture
ATS '14: Proceedings of the 2014 IEEE 23rd Asian Test SymposiumNovember 2014, Pages 336–341https://doi.org/10.1109/ATS.2014.68Scan Compression has become the default design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are now observing Scan Compression improving and adapting to the needs of current ...
- ArticleNovember 2014
Two-Step Dynamic Encoding for Linear Decompressors
ATS '14: Proceedings of the 2014 IEEE 23rd Asian Test SymposiumNovember 2014, Pages 330–335https://doi.org/10.1109/ATS.2014.67In this paper, a new linear decompress or is presented. A specific two-step encoding is incorporated in the implication process to exploit the degree of freedom during ATPG. The proposed decompress or achieves on average 247X test application time ...
- research-articleJune 2014
On Using Implied Values in EDT-based Test Compression
DAC '14: Proceedings of the 51st Annual Design Automation ConferenceJune 2014, Pages 1–6https://doi.org/10.1145/2593069.2593173On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded ...
- ArticleNovember 2012
Multi-level EDT to Reduce Scan Channels in SoC Designs
ATS '12: Proceedings of the 2012 IEEE 21st Asian Test SymposiumNovember 2012, Pages 77–82https://doi.org/10.1109/ATS.2012.70This paper presents a new multi-level EDT scheme to reduce scan channels of scan-based SoC designs. Multi-level EDT requires trivial modification on existing EDT scheme with two-pass encoding. Experimental results show that this scheme can reduce ...
- ArticleAugust 2012
Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme
ICACC '12: Proceedings of the 2012 International Conference on Advances in Computing and CommunicationsAugust 2012, Pages 158–161https://doi.org/10.1109/ICACC.2012.36This paper presents a new approach to reduce both test power and test data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's ...
- research-articleApril 2012
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 2Article No.: 18, Pages 1–24https://doi.org/10.1145/2159542.2159550Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit ...
- ArticleNovember 2011
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)
ATS '11: Proceedings of the 2011 Asian Test SymposiumNovember 2011, Pages 432–437https://doi.org/10.1109/ATS.2011.70Scan compression technology innovation has broken out into solving the data volume problem keeping the test application time gains relatively constant over the generations of technologies. While data volume reductions are important there is a need to ...
- ArticleNovember 2011
Multiscan-based Test Data Compression Using UBI Dictionary and Bitmask
ATS '11: Proceedings of the 2011 Asian Test SymposiumNovember 2011, Pages 279–284https://doi.org/10.1109/ATS.2011.69In this paper, we propose a test data compression method, which combines the advantages of dictionary-based compression and bit mask-based compression. We present a kind of Unfixed-Based Index (UBI), which uses shorter indexes to represent the slices ...
- ArticleNovember 2011
Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination
TRUSTCOM '11: Proceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and CommunicationsNovember 2011, Pages 701–705https://doi.org/10.1109/TrustCom.2011.90Ever-growing test data volume and test power dissipation poses significant cost and security challenges in testing core-based system-on-chip (SoC). In this paper, a test pattern recombination technique is proposed to improve test data compression and ...
- ArticleMay 2011
Reduced ATE Interface for High Test Data Compression
ETS '11: Proceedings of the 2011 Sixteenth IEEE European Test SymposiumMay 2011, Pages 99–104https://doi.org/10.1109/ETS.2011.13This paper presents a study addressing the challenge of interfacing automatic test equipment (ATE) with on-chip decompression logic deployed by system-on-chip designs or modular decompression environments. The ability of the proposed scheme to improve ...
- research-articleMarch 2011
Synthesizing Multiple Scan Trees to Optimize Test Application Time
IEEE Design & Test (DEST), Volume 28, Issue 2March 2011, Pages 62–69https://doi.org/10.1109/MDT.2011.38This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to ...
- research-articleFebruary 2011
Analysis of test data compression techniques emphasizing statistical coding schemes
ICWET '11: Proceedings of the International Conference & Workshop on Emerging Trends in TechnologyFebruary 2011, Pages 1219–1224https://doi.org/10.1145/1980022.1980289In this paper it is observed that the test data compression environment (TDCE) parameters: compression ratio and area overhead of code based data compression techniques in statistical method like Huffman coding, selective Huffman coding, optimal Huffman ...
- research-articleDecember 2010
A low overhead high test compression technique using pattern clustering with n-detection test support
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 18, Issue 12December 2010, Pages 1672–1685https://doi.org/10.1109/TVLSI.2009.2026420This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The ...
- research-articleApril 2010
Multiple scan trees synthesis for test time/data and routing length reduction under output constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 29, Issue 4April 2010, Pages 618–626https://doi.org/10.1109/TCAD.2010.2042896A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time, and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan ...
- research-articleJanuary 2010
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 29, Issue 1January 2010, Pages 117–126https://doi.org/10.1109/TCAD.2009.2035550Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide ...