IEEE Design & Test

This general-interest issue of D&Tfeatures articles on recent advances in design methods such as customization to achieve higher efficiency in terms of power and performance, accurate power estimation for multiprocessor system-on-chips (MPSoCs) based on ...

To meet computing needs and overcome power density limitations, the computing industry has entered the era of parallelization. However, highly parallel, general-purpose computing systems face serious challenges in terms of performance, energy, heat ...

This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and ...

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also ...

Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an ...

Timing-related defects are a major cause of test escapes and field returns for very deep-submicron (VDSM) integrated circuits. Small-delay variations induced by crosstalk, process variations, power supply noise, and resistive opens and shorts can cause ...

This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to ...

This is a review of A Practical Introduction to Hardware/Software Codesign by Patrick R. Schaumont.

This column examines the considerations that underlie how semiconductor manufacturing technologists determine whether a given technology road is worth pursuing.

This month's TTTC newsletter features synopses of past events and of upcoming events.

This month's CEDA Currents newsletter addresses thermal-aware floorplanning for 3D MPSoCs; design automation and Smart Grid II; the IEEE Embedded Systems Letters' most-accessed articles recently; and upcoming CEDA events.

In discussing the profusion of information that test engineers face, The Last Byte compares a test simulator to a movie database. A movie database lets people dive into the mass of movies and find out details about each. Likewise, the simulator lets ...