Export Citations
Publications
Save this search
Please login to be able to save your searches and receive alerts for new content matching your search criteria.
- research-article
Altocumulus: Scalable Scheduling for Nanosecond-Scale Remote Procedure Calls
MICRO '22: Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture•October 2022, pp 423-440• https://doi.org/10.1109/MICRO56248.2022.00039Online services in modern datacenters use Remote Procedure Calls (RPCs) to communicate between different software layers. Despite RPCs using just a few small functions, inefficient RPC handling can cause delays to propagate across the system and ...
- research-article
SEEC: stochastic escape express channel
SC '21: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis•November 2021, Article No.: 34, pp 1-14• https://doi.org/10.1145/3458817.3476140Allocating a free buffer before moving to the next router is a fundamental tenet for packet movement in NoCs. Often, to solve head of line blocking and avoid deadlock, NoCs are provisioned with significant buffer resources in the form of virtual channels ...
- research-article
Mocktails: capturing the memory behaviour of proprietary mobile architectures
ISCA '20: Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture•May 2020, pp 460-472• https://doi.org/10.1109/ISCA45697.2020.00046Computation demands on mobile and edge devices are increasing dramatically. Mobile devices, such as smart phones, incorporate a large number of dedicated accelerators and fixed-function hardware blocks to deliver the required performance and power ...
- survey
Exploiting Errors for Efficiency: A Survey from Circuits to Applications
- Phillip Stanley-Marbell,
- Armin Alaghi,
- Michael Carbin,
- Eva Darulova,
- Lara Dolecek,
- Andreas Gerstlauer,
- Ghayoor Gillani,
- Djordje Jevdjic,
- Thierry Moreau,
- Mattia Cacciotti,
- Alexandros Daglis,
- Natalie Enright Jerger,
- Babak Falsafi,
- Sasa Misailovic,
- Adrian Sampson,
- Damien Zufferey
ACM Computing Surveys, Volume 53, Issue 3•May 2021, Article No.: 51, pp 1-39 • https://doi.org/10.1145/3394898When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from ...
A Primer on Memory Consistency and Cache Coherence
Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory ...
- research-article
UBERNoC: unified buffer power-efficient router for network-on-chip
NOCS '19: Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip•October 2019, Article No.: 1, pp 1-8• https://doi.org/10.1145/3313231.3352362Networks-on-Chip (NoCs) address many shortcomings of traditional interconnects. However, they consume a considerable portion of a chip's total power - particularly when the utilization is low. As transistor size continues to shrink, we expect NoCs to ...
- research-article
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution
MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture•October 2019, pp 873-885• https://doi.org/10.1145/3352460.3358255An interconnection network forms the communication backbone in both on-chip and off-chip systems. In networks, congestion causes packets to be blocked. Indefinite blocking can occur if cyclic dependencies exist, leading to deadlock. All modern networks ...
- research-article
CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs
IEEE Transactions on Computers, Volume 68, Issue 9•Sept. 2019, pp 1283-1296 • https://doi.org/10.1109/TC.2019.2906869Modern GPUs feature an increasing number of streaming multiprocessors (SMs) to boost system throughput. How to construct an efficient and scalable network-on-chip (NoC) for future high-performance GPUs is particularly critical. Although a mesh network is ...
- research-article
The EH model: early design space exploration of intermittent processor architectures
MICRO-51: Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture•October 2018, pp 600-612• https://doi.org/10.1109/MICRO.2018.00055Energy-harvesting devices---which operate solely on energy collected from their environment---have brought forth a new paradigm of intermittent computing. These devices succumb to frequent power outages that would cause conventional systems to be stuck ...
- research-article
SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers
ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design•July 2018, Article No.: 17, pp 1-6• https://doi.org/10.1145/3218603.3218635Due to high aggregate idle time of Networks-on-Chip (NoCs) routers in practical applications, power-gating techniques have been proposed to combat the ever-increasing ratio of static power. Nevertheless, the sporadic packet arrivals compromise the ...
- research-article
Modular routing design for chiplet-based systems
- Jieming Yin,
- Zhifeng Lin,
- Onur Kayiran,
- Matthew Poremba,
- Muhammad Shoaib Bin Altaf,
- Natalie Enright Jerger,
- Gabriel H. Loh
ISCA '18: Proceedings of the 45th Annual International Symposium on Computer Architecture•June 2018, pp 726-738• https://doi.org/10.1109/ISCA.2018.00066System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to ...
- research-article
Fast and Accurate Performance Analysis of Synchronization
PMAM'18: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores•February 2018, pp 31-40• https://doi.org/10.1145/3178442.3178446Understanding parallel program bottlenecks is critical to designing more efficient and performant parallel architectures. Synchronization is a prime example of a potential bottleneck, but is a necessary evil when writing parallel programs; we must ...
- research-article
The EH Model: Analytical Exploration of Energy-Harvesting Architectures
IEEE Computer Architecture Letters, Volume 17, Issue 1•January 2018, pp 76-79 • https://doi.org/10.1109/LCA.2017.2777834Energy-harvesting devices—which operate solely on energy collected from their environment—have brought forth a new paradigm of intermittent computing. These devices succumb to frequent power outages that would cause conventional systems to be stuck in a ...
On-Chip Networks: Second Edition
This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. ...
- research-article
The bunker cache for spatio-value approximation
MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture•October 2016, Article No.: 43, pp 1-12The cost of moving and storing data is still a fundamental concern for computer architects. Inefficient handling of data can be attributed to conventional architectures being oblivious to the nature of the values that these data bits carry. We observe ...
- research-article
The anytime automaton
ISCA '16: Proceedings of the 43rd International Symposium on Computer Architecture•June 2016, pp 545-557• https://doi.org/10.1109/ISCA.2016.54Approximate computing is an emerging paradigm enabling tradeoffs between accuracy and efficiency. However, a fundamental challenge persists: state-of-the-art techniques lack the ability to enforce runtime guarantees on accuracy. The convention is to 1) ...
Also Published in:
ACM SIGARCH Computer Architecture News: Volume 44 Issue 3, June 2016 - research-article
Cnvlutin: ineffectual-neuron-free deep neural network computing
ISCA '16: Proceedings of the 43rd International Symposium on Computer Architecture•June 2016, pp 1-13• https://doi.org/10.1109/ISCA.2016.11This work observes that a large fraction of the computations performed by Deep Neural Networks (DNNs) are intrinsically ineffectual as they involve a multiplication where one of the inputs is zero. This observation motivates Cnvlutin (CNV), a value-...
Also Published in:
ACM SIGARCH Computer Architecture News: Volume 44 Issue 3, June 2016 - research-article
Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks
- Patrick Judd,
- Jorge Albericio,
- Tayler Hetherington,
- Tor M. Aamodt,
- Natalie Enright Jerger,
- Andreas Moshovos
ICS '16: Proceedings of the 2016 International Conference on Supercomputing•June 2016, Article No.: 23, pp 1-12• https://doi.org/10.1145/2925426.2926294This work exploits the tolerance of Deep Neural Networks (DNNs) to reduced precision numerical representations and specifically, their recently demonstrated ability to tolerate representations of different precision per layer while maintaining accuracy. ...
- research-article
Hierarchical Clustering for On-Chip Networks
AISTECS '16: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems•January 2016, Article No.: 2, pp 1-6• https://doi.org/10.1145/2857058.2857064Hierarchy and communication locality are a must for many-core systems. As systems scale to dozens or hundreds of cores, we simply cannot afford the power consumption and latency of random communication that spans the entire chip. Existing hierarchical ...
