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- research-articleSeptember 2024
LLM Based Physical Verification Runset Generator
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 35, Pages 1–7https://doi.org/10.1145/3670474.3685976The complexity in design rule description and coding is drastically increasing as technology nodes advance. This complexity makes the process of implementing the physical verification (PV) rule checks more time-consuming and susceptible to human error, ...
- research-articleSeptember 2024
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 34, Pages 1–7https://doi.org/10.1145/3670474.3685975Exploding predictive AI has enabled fast yet effective evaluation and decision-making in modern chip physical design flows. State-of-the-art frameworks typically include the objective of minimizing the mean square error (MSE) between the prediction and ...
- invited-talkSeptember 2024
LLM-Assisted Analytics in Semiconductor Test (Invited)
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 38, Pages 1–7https://doi.org/10.1145/3670474.3685974The emergence of Large Language Models (LLMs) has impacted our perspective on applying Machine Learning (ML) in semiconductor test. This paper shares our experience in leveraging the power of LLMs to build an AI agent for test data analytics. We advocate ...
- invited-talkSeptember 2024
When Device Modeling Meets Machine Learning: Opportunities and Challenges (Invited)
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 36, Pages 1–6https://doi.org/10.1145/3670474.3685972Device modeling is essential for circuit simulations and designs in terms of constructing the circuit matrix equations of KCL and KVL. While there are classical methodologies, machine learning techniques are promising to bring innovations in the ...
- research-articleSeptember 2024
Human Language to Analog Layout Using GLayout Layout Automation Framework
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 33, Pages 1–7https://doi.org/10.1145/3670474.3685971Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an ...
Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 32, Pages 1–8https://doi.org/10.1145/3670474.3685970Machine learning (ML) has proved useful across a wide range of applications in the very-large-scale integration computer-aided design (VLSI CAD) domain. To avoid overestimating ML models' generalization capabilities for real-world deployments, best ...
Enabling Risk Management of Machine Learning Predictions for FPGA Routability
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 31, Pages 1–9https://doi.org/10.1145/3670474.3685969Machine Learning (ML) models sometimes make inaccurate predictions for the routability of field-programmable gate array (FPGA) circuit designs. This risks time wasted attempting to route an unroutable design or the premature termination of a routable ...
- research-articleSeptember 2024
ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 30, Pages 1–9https://doi.org/10.1145/3670474.3685968Integrated circuits at advanced technology nodes are prone to process variations and early life failures due to aging. Variations in transistor parameters lead to a degraded on-current which, in turn, results in increasing gate-level propagation delay. ...
- research-articleSeptember 2024
LASP: LLM Assisted Security Property Generation for SoC Verification
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 29, Pages 1–7https://doi.org/10.1145/3670474.3685967As the complexity of System-on-Chips (SoCs) increases, ensuring their security presents escalating challenges. Formal property verification is one of the most robust methods to model and check security behaviors using model checkers. However, the ...
- research-articleSeptember 2024
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
- Prashanth Vijayaraghavan,
- Apoorva Nitsure,
- Charles Mackin,
- Luyao Shi,
- Stefano Ambrogio,
- Arvind Haran,
- Viresh Paruthi,
- Ali Elzein,
- Dan Coops,
- David Beymer,
- Tyler Baldwin,
- Ehsan Degan
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 28, Pages 1–10https://doi.org/10.1145/3670474.3685966Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Automation (EDA), LLMs show promise for tasks like Register-Transfer Level (...
- research-articleSeptember 2024
Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 27, Pages 1–7https://doi.org/10.1145/3670474.3685965The composite current source (CCS) model has been adopted as an advanced timing model that represents the current behavior of cells for improved accuracy and better capability than traditional non-linear delay models (NLDM) to model complex dynamic ...
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 26, Pages 1–11https://doi.org/10.1145/3670474.3685964Large Language Models (LLMs) are effective in computer hardware synthesis via hardware description language (HDL) generation. However, LLM-assisted approaches for HDL generation struggle when handling complex tasks. We introduce a suite of hierarchical ...
MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 24, Pages 1–8https://doi.org/10.1145/3670474.3685962The initial steps of logic synthesis of digital designs involve finding minimized representations of Boolean logic functions. Existing optimization methods rely on iterative minimization operations that can result in a rapid increase in the runtime when ...
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
- Stefan Abi-Karam,
- Rishov Sarkar,
- Allison Seigler,
- Sean Lowe,
- Zhigang Wei,
- Hanqiu Chen,
- Nanditha Rao,
- Lizy John,
- Aman Arora,
- Cong Hao
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 23, Pages 1–9https://doi.org/10.1145/3670474.3685961Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible high-quality HLS datasets and the complexity of ...
- research-articleSeptember 2024
Efficient Subgraph Matching Framework for Fast Subcircuit Identification
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 20, Pages 1–7https://doi.org/10.1145/3670474.3685958Subcircuit identification finds wide applications in logic synthesis, physical design, and design verification. With the continuous increase in the scale of integrated circuits, the exploration of efficient identification algorithms has become a key ...
- research-articleSeptember 2024
TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 19, Pages 1–7https://doi.org/10.1145/3670474.3685957In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D Integrated Circuits (ICs). Recent advancements in 3D vertical interconnection technology ...
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 18, Pages 1–10https://doi.org/10.1145/3670474.3685956In digital circuit design, testbenches (TBs) constitute the cornerstone of simulation-based hardware verification. Traditional methodologies for testbench generation during simulation-based hardware verification still remain partially manual, resulting ...
- research-articleSeptember 2024
High-Dimensional Yield Analysis Using Sparse Representation for Long-Tailed Distribution
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 16, Pages 1–7https://doi.org/10.1145/3670474.3685954With more advanced technology nodes and stringent robustness requirements, fast, accurate, and universal yield analysis for custom circuits in the early design stage becomes a key bottleneck for manufacturing. In this paper, we propose a sparse ...
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 14, Pages 1–12https://doi.org/10.1145/3670474.3685952In recent years, domain-specific accelerators (DSAs) have gained popularity for applications such as deep learning and autonomous driving. To facilitate DSA designs, programmers use high-level synthesis (HLS) to compile a high-level description written ...
Automated Physical Design Watermarking Leveraging Graph Neural Networks
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADSeptember 2024, Article No.: 13, Pages 1–10https://doi.org/10.1145/3670474.3685951This paper presents AutoMarks, an automated and transferable watermarking framework that leverages graph neural networks to reduce the watermark search overheads during the placement stage. AutoMarks's novel automated watermark search is accomplished by (...