Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is ...
Timing modeling and optimization under the transmission line model
As the operating frequency increases to gigahertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a wire, it is necessary to consider the transmission line behavior for delay computation. We present in this paper, ...
Timing driven gate duplication
In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication ...
A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm
The use of online arithmetic was often proposed for hardware implementations of complex digital-signal processing (DSP) algorithms. However, several important issues in the design process of such algorithms using online arithmetic are rarely discussed ...
Substrate coupling in digital circuits in mixed-signal smart-power systems
- Radu M. Secareanu,
- Scott Warner,
- Scott Seabridge,
- Cathie Burke,
- Juan Becerra,
- Thomas E. Watrobski,
- Christopher Morton,
- William Staub,
- Thomas Tellier,
- Ivan S. Kourtev,
- Eby G. Friedman
This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-...
A jitter characterization system using a component-invariant vernier delay line
Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter ...
Managing power consumption in networks on chips
In this paper, we present a new methodology for managing power consumption of networks-on-chips (NOCs). A power management problem is formulated for the first time using closed-loop control concepts. We introduce an estimator and a controller that ...
On-chip traffic modeling and synthesis for MPEG-2 video applications
The objective of this paper is to introduce self-similarity as a fundamental property exhibited by the bursty traffic between on-chip modules in typical MPEG-2 video applications. Statistical tests performed on relevant traces extracted from common ...
A fast on-chip profiler memory using a pipelined binary tree
We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used ...
