Special section on international symposium on networks-on-chip (NOCS)
The idea for this special section started with the intention to archive the top papers from the First ACM/IEEE International Symposium on Networks on Chips (NOCS) in 2007. The first two papers tackle the tight power constraints of on-chip network ...
An energy and performance exploration of network-on-chip architectures
In this paper, we explore the designs of a circuit -switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they ...
Design and management of voltage-frequency island partitioned networks-on-chip
The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) ...
Custom networks-on-chip architectures with multicast routing
In this paper, we consider the problem of synthesizing custom networks-on-chip (NoC) architectures that are optimized for a given application. We consider both unicast and multicast traffic flows in the input specification. Multicast traffic flows are ...
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)] to provide the required communication performance to applications. Implementing NoC using table-based switches provide many advantages, including possibility ...
81.6 GOPS object recognition processor based on a memory-centric NoC
For mobile intelligent robot applications, an 81.6 GOPS object recognition processor is implemented. Based on an analysis of the target application, the chip architecture and hardware features are decided. The proposed processor aims to support both ...
A case study for NoC-based homogeneous MPSoC architectures
The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the ...
Design optimization of time-and cost-constrained fault-tolerant embedded systems with checkpointing and replication
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are ...
Optimal periodic memory allocation for image processing with multiple windows
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents an efficient memory allocation to minimize the number of memory modules and processing ...
Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding
This paper presents an efficient VLSI architecture for H.264/AVC content-adaptive binary arithmetic code (CABAC) decoding. We introduce several new techniques to maximize the parallelism of the decoding process, including variable-bin-rate strategy, ...
Power management of voltage/frequency island-based systems using hardware-based methods
Shrinking technology nodes combined with the need for higher clock speeds have made it increasingly difficult to distribute a single global clock across a chip while meeting the power requirements of the design. Globally asynchronous locally synchronous ...
Design of voltage overscaled low-power trellis decoders in presence of process variations
In hardware implementations of many signal processing functions, timing errors on different circuit signals may have largely different importance with respect to the overall signal processing performance. This motivates us to apply the concept of ...
Fast scaling in the residue number system
A new scheme for precisely scaling numbers in the residue number system (RNS) is presented. The scale factor K can be any number coprime to the RNS moduli. Lookup table implementations are used as a basis for comparisons between the new scheme and ...
Fully monolithic cellular buck converter design for 3-D power delivery
A fully monolithic interleaved buck dc-dc point-of-load (PoL) converter has been designed and fabricated in a 0.18-mm SiGe BiCMOS process. Target application of the design is 3-D power delivery for future microprocessors, in which the PoL converter will ...
