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Design of voltage overscaled low-power trellis decoders in presence of process variations

Published: 01 March 2009 Publication History
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  • Abstract

    In hardware implementations of many signal processing functions, timing errors on different circuit signals may have largely different importance with respect to the overall signal processing performance. This motivates us to apply the concept of unequal error tolerance to enable the use of voltage overscaling at minimal signal processing performance degradation. Realization of unequal error tolerance involves two main issues, including how to quantify the importance of each circuit signal and how to incorporate the importance quantification into signal processing circuit design. We developed techniques to tackle these two issues and applied them to two types of trellis decoders including Viterbi decoder for convolutional code decoding and Max-Log-Maximum A Posteriori (MAP) decoder for Turbo code decoding. Simulation results demonstrated promising energy saving potentials of the proposed design solution on both trellis decoding computation and memory storage at small decoding performance degradation.

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      Published In

      cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
      IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 17, Issue 3
      March 2009
      137 pages

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      IEEE Educational Activities Department

      United States

      Publication History

      Published: 01 March 2009
      Revised: 08 February 2008
      Received: 09 October 2007

      Author Tags

      1. Clock skew scheduling
      2. clock skew scheduling
      3. low-power
      4. process variations
      5. trellis decoders
      6. unequal error tolerance
      7. voltage overscaling (VOS)

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      • (2014)A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless ReceiversACM Transactions on Embedded Computing Systems10.1145/258466613:4s(1-29)Online publication date: 1-Apr-2014

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