Authenticated encryption on FPGAs from the static part to the reconfigurable part
Recently, techniques have been invented to combine encryption and authentication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces smaller area compared to two separate ...
A framework for reliability-aware embedded system design on multiprocessor platforms
This paper presents a model-driven framework that provides a tool-supported design flow for fault-tolerant embedded systems. Its system models comprise abstract descriptions of the application and the underlying execution platform. They provide the ...
Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies
In this paper, a comprehensive study is first conducted to investigate the effects of cache coherence protocols and cache replacement policies on the characteristics of NUCA in current many-core processors. The main focus of this study is to analyze the ...
A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems
This paper presents a methodology for the system-level dependability analysis of multiprocessor embedded systems. The methodology is based on fault injection and features an error analysis approach offering to the designer the possibility to specify ...
Exploiting processor features to implement error detection in reduced precision matrix multiplications
Modern processors incorporate complex arithmetic units that can work with large word-lengths. Those units are useful for applications that require high precision. There are however, many applications for which the use of reduced precision is sufficient. ...
Multiple detection test generation with diversified fault partitioning paths
The dependability of current and future nanoscale technologies highly depends on the ability of the testing process to detect emerging defects that cannot be modeled traditionally. Generating test sets that detect each fault more than one times has been ...
Bit Impact Factor: Towards making fair vulnerability comparison
Reliability is becoming a major design concern in contemporary microprocessors since soft error rate is increasing due to technology scaling. Therefore, design time system vulnerability estimation is of paramount importance. Architectural Vulnerability ...
A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices
This paper presents a new method and results from measurement of internal parameters of programmable nanoscale circuits, namely Xilinx FPGA devices and especially Zynq SoC devices designed on 28nm TSMC's technology and older 45nm Spartan 6 device as ...
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip
- Michael Dimopoulos,
- Yi Gang,
- Lorena Anghel,
- Mounir Benabdenbi,
- Nacer-Eddine Zergainoh,
- Michael Nicolaidis
An online fault tolerant routing algorithm for 2D mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime permanent and ...
