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- posterMay 2014
Trade-off between energy and quality of service through dynamic operand truncation and fusion
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 79–80https://doi.org/10.1145/2591513.2591561Energy efficiency has emerged as a major design concern for embedded and portable electronics. Conventional approaches typically impact performance and often require significant design-time modifications. In this paper, we propose a novel approach for ...
- posterMay 2014
Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 73–74https://doi.org/10.1145/2591513.2591555FinFET has been proposed as an alternative for bulk CMOS in the ultra-low power designs due to its more effective channel control, reduced random dopant fluctuation, higher ON/OFF current ratio, lower energy consumption, etc. The characteristics of ...
- research-articleMay 2014
A novel parallel adaptation of an implicit path delay grading method
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 217–222https://doi.org/10.1145/2591513.2591539For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit ...
- research-articleMay 2014
MB-FICA: multi-bit fault injection and coverage analysis
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 205–210https://doi.org/10.1145/2591513.2591538Recent studies have shown a dramatic increase in multi-bit upset (MBU) events and related errors as transistors continue to shrink.
To assist designers with addressing MBU in microprocessor register files, we have extended an architectural description ...
- research-articleMay 2014
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 3–8https://doi.org/10.1145/2591513.2591531The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the presence and propagation of transient faults. If these faults are latched, they will corrupt data validity and can make the whole circuit to stall, ...
- research-articleMay 2014
Reliability-aware cross-point resistive memory design
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 145–150https://doi.org/10.1145/2591513.2591528The transition metal oxide (TMO) resistive random access memory (ReRAM) has been identified as one of the most promising candidates for the next generation non-volatile memory (NVM) technology. Numerous TMO ReRAMs with different materials have been ...
- research-articleMay 2014
WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 139–144https://doi.org/10.1145/2591513.2591525Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased. Since SRAM consumes high leakage power, researchers have explored use of non-volatile memories (NVMs) for designing ...
- research-articleMay 2014
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 311–316https://doi.org/10.1145/2591513.2591522This paper presents a novel digitally-assisted automatic frequency tuning technique, and the self calibration technique is verified for a 130nm CMOS 4th order biquad baseband low-pass filter case with 20MHz cut-off frequency, which satisfies the typical ...
- research-articleMay 2014
System-level reliability exploration framework for heterogeneous MPSoC
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 9–14https://doi.org/10.1145/2591513.2591519Power density of digital circuits increased at alarming rate for deep sub-micron CMOS technology, turning reliability into a serious design concern. On the other hand, ever-growing task complexity with strict performance budget forced designers to adopt ...
- research-articleMay 2014
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 211–216https://doi.org/10.1145/2591513.2591518Asynchronous networks on chip (NoCs) are promising candidates for supporting the enormous communication needed by future many-core systems due to their low-energy and high-speed. Similar to synchronous NoCs, asynchronous NoCs are vulnerable to faults ...
- posterMay 2014
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIMay 2014, Pages 91–92https://doi.org/10.1145/2591513.2591571Post-Silicon clock-Skew Tuning (PSST) is a promising technology for improving performance-yield of VLSIs under process variations. On the other hand, the resultant circuit after PSST should be also robust for run-time timing variations due to the change ...