Cited By
View all- Pomeranz I(2020)Non-Masking Non-Robust Tests for Path Delay Faults2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107556(1-6)Online publication date: Apr-2020
A novel parallel adaptation of an implicit path delay grading method
Pages 217 - 222
Abstract
For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit path delay fault grading on with a GPGPU implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50x speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200x speedup is observed against a single-threaded, more complex version in the framework which grades more faults.
References
[1]
M. Bushnell and V. Agrawal, Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer Academic, 2000.
[2]
S. Natarajan, S. Patil, and S. Chakravarty, "Path delay fault simulation on large industrial designs," in Proceedings of the 24th IEEE VLSI Test Symposium, 2006., April-4 May 2006, p. 6.
[3]
A. Majhi and V. Agrawal, "Delay fault models and coverage," in Proceedings of Eleventh International Conference on VLSI Design, Jan 1998, pp. 364--369.
[4]
C. J. Lin and S. Reddy, "On delay fault testing in logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 5, pp. 694--703, September 1987.
[5]
M. Schulz, F. Fink, and K. Fuchs, "Parallel pattern fault simulation of path delay faults," June 1989, pp. 357--363.
[6]
T. W. Williams, B. Underwood, and M. R. Mercer, "The interdependence between delay-optimization of synthesized networks and testing," ser. DAC '91. ACM, 1991, pp. 87--92. {Online}. Available: http://doi.acm.org/10.1145/127601.127633
[7]
M. Schulz, K. Fuchs, and F. Fink, "Advanced automatic test pattern generation techniques for path delay faults," in Nineteenth International Symposium on Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., 1989, pp. 44--51.
[8]
D. Kagaris and S. Tragoudas, "On the nonenumerative path delay fault simulation problem," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 21, no. 9, pp. 1095--1101, Sep 2002.
[9]
F. Kocan and M. Gunes, "On the zbdd-based nonenumerative path delay fault coverage calculation," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, no. 7, pp. 1137--1143, July 2005.
[10]
S. Padmanaban, M. Michael, and S. Tragoudas, "Exact path delay grading with fundamental bdd operations," in Proceedings of International Test Conference, 2001, 2001, pp. 642--651.
[11]
S. Padmanaban and S. Tragoudas, "An implicit path-delay fault diagnosis methodology," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, no. 10, pp. 1399--1408, oct. 2003.
[12]
M. Sivaraman and A. Strojwas, "Path delay fault diagnosis and coverage-a metric and an estimation technique," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, no. 3, pp. 440--457, Mar 2001.
[13]
I. Pomeranz and S. Reddy, "An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 2, pp. 240--250, Feb 1994.
[14]
M. Kumar, S. Tragoudas, S. Chakravarty, and R. Jayabharathi, "Implicit and exact path delay fault grading in sequential circuits," in Proceedings of Design, Automation and Test in Europe, 2005, March 2005, pp. 990--995 Vol. 2.
[15]
D. Kagaris, S. Tragoudas, and D. Karayiannis, "Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 309--315, Mar 1997.
[16]
K. Heragu, V. Agrawal, M. Bushnell, and J. Patel, "Improving anonenumerative method to estimate path delay fault coverage," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 759--762, Jul 1997.
[17]
S. Baxter. (2013) Modern gpu. www. NVIDIA Corporation. {Online}. Available: http://nvlabs.github.io/moderngpu/
[18]
M. Li and M. Hsiao, "3-d parallel fault simulation with gpgpu," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, no. 10, pp. 1545--1555, oct. 2011.
[19]
D. Chatterjee, A. DeOrio, and V. Bertacco, "Event-driven gate-level simulation with gp-gpus," in 46th ACM/IEEE Design Automation Conference, 2009. DAC '09, July 2009, pp. 557--562.
[20]
Y. Zhu, B. Wang, and Y. Deng, "Massively parallel logic simulation with gpus," ACM Trans. Des. Autom. Electron. Syst., vol. 16, no. 3, pp. 29:1--29:20, Jun. 2011. {Online}. Available: http://doi.acm.org/10.1145/1970353.1970362
[21]
R. Raghavan, J. Hayes, and W. Martin, "Logic simulation on vector processors," in IEEE International Conference on Computer-Aided Design, 1988. ICCAD-88., Nov 1988, pp. 268--271.
[22]
M. Harris. (2007, April) Parallel prefix sum (scan) with cuda. www. nVidia. {Online}. Available: http://developer.download.nvidia.com/compute/cuda/11/Website/projects/scan/doc/scan.pdf
[23]
C. Group. Cad group: Itc'99 benchmarks (2nd release). Politecnico di Torino. {Online}. Available: http://www.cad.polito.it/downloads/tools/itc99.html
Index Terms
- A novel parallel adaptation of an implicit path delay grading method
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Published In
May 2014
376 pages
ISBN:9781450328166
DOI:10.1145/2591513
- General Chairs:
- Joseph R. Cavallaro,
- Tong Zhang,
- Program Chairs:
- Alex K. Jones,
- Hai (Helen) Li
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Published: 20 May 2014
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View all- Pomeranz I(2020)Non-Masking Non-Robust Tests for Path Delay Faults2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107556(1-6)Online publication date: Apr-2020
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