Abstract
Leakage power has been a significant concern in power constrained processor design as manufacturing technology has scaled down dramatically in the last decades. While power gating has been known to deliver leakage power reductions, its success has heavily relied on judicious power gating decisions. Yet delivering such prudent decisions has been particularly challenging for out-of-order processors due to the unpredictability of execution order. This paper introduces an intelligent power gating method for out-of-order embedded and mobile processor execution units by monitoring and utilizing readily available hints on the pipeline. First, we track the counts of different instruction types in the instruction queue to identify the execution units slated to remain idle in the near future. As the presence of an instruction is not a definite indicator of its execution start due to stalls, our second guidance improves the accuracy of the first approach by tracking the stalling instructions in the instruction queue due to memory dependencies. While tracking IQ content delivers dramatically better results than the state-of-the-art timeout-based methods in the literature with 48.8% energy reductions, the memory-aware guidance boosts energy savings up to 72.8% on average for memory intensive applications.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Rupley, J.: Samsung M3 processor. In: 2018 IEEE Hot Chips 30 Symposium (HCS), Cupertino, CA, USA (2018)
Halpern, M., Zhu, Y., Reddi, V.J.: Mobile CPU’s rise to power: quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction. In: 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 64–76 (2016). https://doi.org/10.1109/HPCA.2016.7446054
Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings 28th Annual International Symposium on Computer Architecture, pp. 240–251 (2001). https://doi.org/10.1109/ISCA.2001.937453
Chaver, D., Piñuel, L., Prieto, M., Tirado, F., Huang, M.C.: Branch prediction on demand: an energy-efficient solution. In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 390–395 (2003). https://doi.org/10.1145/871506.871603
Leverich, J., Monchiero, M., Talwar, V., Ranganathan, P., Kozyrakis, C.: Power management of datacenter workloads using per-core power gating. IEEE Comput. Archit. Lett. 8, 48–51 (2009). https://doi.org/10.1109/L-CA.2009.46
Kaxiras, S., Martonosi, M.: Computer architecture techniques for power-efficiency. In: Synthesis Lectures on Computer Architecture (2008). https://doi.org/10.2200/S00119ED1V01Y200805CAC004
Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural techniques for power gating of execution units. In: International Symposium on Low Power Electronics and Design, pp. 32–37 (2004). https://doi.org/10.1145/1013235.1013249
Bournoutian, G., Orailoglu, A.: Mobile ecosystem driven dynamic pipeline adaptation for low power. In: Pinho, L.M.P., Karl, W., Cohen, A., Brinkschulte, U. (eds.) ARCS 2015. LNCS, vol. 9017, pp. 83–95. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-16086-3_7
Jeong, K., Kahng, A.B., Kang, S., Rosing, T.S., Strong, R.: MAPG: memory access power gating. In: Design, Automation & Test in Europe Conference (DATE), pp. 1054–1059 (2012)
Kahng, A.B., Kang, S., Rosing, T., Strong, R.: TAP: token-based adaptive power gating. In: International Symposium on Low Power Electronics and Design, pp. 203–208 (2012). https://doi.org/10.1145/2333660.2333711
Rele, S., Pande, S., Onder, S., Gupta, R.: Optimizing static power dissipation by functional units in superscalar processors. In: Horspool, R.N. (ed.) CC 2002. LNCS, vol. 2304, pp. 261–275. Springer, Heidelberg (2002). https://doi.org/10.1007/3-540-45937-5_19
You, Y.-P., Lee, C., Lee, J.K.: Compilers for leakage power reduction. ACM Trans. Des. Autom. Electron. Syst. 11, 147–164 (2006). https://doi.org/10.1145/1124713.1124723
Roy, S., Ranganathan, N., Katkoori, S.: A framework for power-gating functional units in embedded microprocessors. IEEE Tran. Very Large Scale Integr. (VLSI) Syst. 17, 1640–1649 (2009). https://doi.org/10.1109/TVLSI.2008.2005774
Kondo, M., et al.: Design and evaluation of fine-grained power-gating for embedded microprocessors. In: Design, Automation & Test in Europe Conference (DATE), pp. 145:1–145:6 (2014). https://doi.org/10.7873/DATE.2014.158
Bahar, R.I., Manne, S.: Power and energy reduction via pipeline balancing. In: 28th Annual International Symposium on Computer Architecture, pp. 218–229 (2001). https://doi.org/10.1109/ISCA.2001.937451
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 5th edn, Appendix H. Elsevier (2011)
Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News. 39, 1–7 (2011). https://doi.org/10.1145/2024716.2024718
Chiu, K.W., Chen, Y.G., Lin, I.C.: An efficient NBTI-aware wake-up strategy for power-gated designs. In: Design, Automation & Test in Europe Conference (DATE), pp. 901–904 (2018). https://doi.org/10.23919/DATE.2018.8342136
Li, S., Ahn, J.H., Strong, R.D., Brockman, J.B., Tullsen, D.M., Jouppi, N.P.: McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469–480 (2009). https://doi.org/10.1145/1669112.1669172
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Ozen, E., Orailoglu, A. (2019). The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_19
Download citation
DOI: https://doi.org/10.1007/978-3-030-18656-2_19
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-18655-5
Online ISBN: 978-3-030-18656-2
eBook Packages: Computer ScienceComputer Science (R0)