Article

Power and energy reduction via pipeline balancing

Authors:

Srilatha ManneAuthors Info & Claims

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture

Pages 218 - 229

https://doi.org/10.1145/379240.379265

Published: 01 May 2001 Publication History

Abstract

Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.

References

[1]

D. Albonesi. Dynamic IPC/clock rate optimization. In Proceedings of the International Symposium on Computer A rchitecture, June 1998.

Digital Library

[2]

D. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proceedings of the International Symposium on Microarchitecture, November 1999.

Digital Library

[3]

V. Arasanipalai. Private communication, Compaq Computer Corporation.

[4]

T. Burd Processor design for portable systems. Journal of VLSI Signal Processing, August 1996.

Digital Library

[5]

G. Chrysos and J. Emer. Memory dependence prediction using store sets. In Proceedings of the International Symposium on Computer Architecture, June 1998.

Digital Library

[6]

Compaq Computer Corporation. Alpha 21264 Microprocessor Hardware Reference Manual, July 1999.

[7]

Compaq Computer Corporation. The AS1M Manual, August 2000.

[8]

J.L. Cruz, A. Gonzalez, M. Valero, and N. Topham. Multiplebanked register file architectures. In Proceedings of the International Symposium on Computer Architecture, June 2000.

Digital Library

[9]

J. A. Farrell and T. C. Fischer. Issue logic for a 600-mhz outof-order execution microprocessor. IEEE Journal of Solid- State Circuits, May 1998.

[10]

S. Ghiasi, J. Casmira, and D. Grunwald. Using 1PC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexi~. -Effective Design, June 2000. Held in conjunction with the International Symposium on Computer Architecture.

[11]

P. N. Glaskowsky. Pentium 4 (partially) previewed. Microprocessor Report, August 2000.

[12]

M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of the Design Automation Conference ( DAC), June 1998.

Digital Library

[13]

D. Grunwald, A. Klauser, S. Manne, and A. Pleszkun. Confidence estimation for speculation control. In Proceedblgs of the International Symposium on Computer Architecture, June 1998.

Digital Library

[14]

S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the International Symposium on Computer Architecture, June 1998.

Digital Library

[15]

J. S. Seng, D. M. Tullsen, and G. Z. N. Cai. Power-sensitive multithreaded architecture. In Proceedings of the International Conference on Computer Design, October 2000.

Digital Library

[16]

A. Snavely and D. M. Tullsen. Symbiotic jobscheduling lor a simultaneous multithreading architecture. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.

Digital Library

[17]

D. W. Wall. Limits of instuction-level parallelism. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 1991.

Digital Library

[18]

K. Wilcox and S. Manne. Alpha processors: A history of power issues and a look to the future. In Cool-Chips Tutorial, November 1999. Held in conjunction with the International Symposium on Microarchitecture.

Cited By

Owahid AJohn E(2023)Instruction Profiling Based Predictive Throttling for Power and PerformanceIEEE Transactions on Computers10.1109/TC.2023.330607972:12(3532-3545)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TC.2023.3306079
Bhattacharjee PTrivedi GMajumder A(2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493(1-20)Online publication date: 28-Dec-2022
https://doi.org/10.1080/00207217.2022.2158493
Tarsa SChowdhury RSebot JChinya GGaur JSankaranarayanan KLin CChappell RSinghal RWang HManne SHunter HAltman E(2019)Post-silicon CPU adaptation made practical using machine learningProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322267(14-26)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322267
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Power and energy reduction via pipeline balancing

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Published In

cover image ACM Conferences

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture

June 2001

289 pages

ISBN:0769511627

DOI:10.1145/379240

Chairman:
Per Stenström
Chalmers Univ. of Technology

ACM SIGARCH Computer Architecture News Volume 29, Issue 2
Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)
May 2001
262 pages
ISSN:0163-5964
DOI:10.1145/384285
Editor:
Per Stenström
Chalmers Univ. of Technology
Issue’s Table of Contents

Copyright © 2001 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\TCCA: TC on Computer Arhitecture

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Association for Computing Machinery

New York, NY, United States

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Published: 01 May 2001

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ISCA01

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ISCA01: 28th International Symposium on Computer Architecture

June 30 - July 4, 2001

Göteborg, Sweden

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ISCA '01 Paper Acceptance Rate 24 of 163 submissions, 15%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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The 52nd Annual International Symposium on Computer Architecture

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Cited By

Owahid AJohn E(2023)Instruction Profiling Based Predictive Throttling for Power and PerformanceIEEE Transactions on Computers10.1109/TC.2023.330607972:12(3532-3545)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TC.2023.3306079
Bhattacharjee PTrivedi GMajumder A(2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493(1-20)Online publication date: 28-Dec-2022
https://doi.org/10.1080/00207217.2022.2158493
Tarsa SChowdhury RSebot JChinya GGaur JSankaranarayanan KLin CChappell RSinghal RWang HManne SHunter HAltman E(2019)Post-silicon CPU adaptation made practical using machine learningProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322267(14-26)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322267
Kayiran OJog APattnaik AAusavarungnirun RTang XKandemir MLoh GMutlu ODas CZaks AMendelson BRauchwerger LHwu W(2016)μC-StatesProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967941(17-30)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2967941
Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Jha SHeirman WFalcón ACarlson TVan Craeynest KTubella JGonzález AEeckhout LNapoli CSalapura VFranke HHou R(2015)ChryssoProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742885(1-8)Online publication date: 6-May-2015
https://dl.acm.org/doi/10.1145/2742854.2742885
Endo FCouroussé DCharles H(2015)Micro-architectural simulation of embedded core heterogeneity with gem5 and McPATProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693440(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693440
Lv PXiao JShi S(2014)A Novel Compiler Assisted Approach for Issue Queue Power ReductionApplied Mechanics and Materials10.4028/www.scientific.net/AMM.543-547.1981543-547(1981-1986)Online publication date: Mar-2014
https://doi.org/10.4028/www.scientific.net/AMM.543-547.1981
Lukefahr APadmanabha SDas RDreslinski RWenisch TMahlke SAmaral JTorrellas J(2014)Heterogeneous microarchitectures trump voltage scaling for low-power coresProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628078(237-250)Online publication date: 24-Aug-2014
https://dl.acm.org/doi/10.1145/2628071.2628078
Zhang WZhang HLach JXie YKarnik TKhellah MMehra R(2014)Adaptive front-end throttling for superscalar processorsProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627633(21-26)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2627633
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