Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

  • Review Article
  • Published:

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Nature volume 479, pages 310–316 (2011)Cite this article

Subjects

Abstract

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

This is a preview of subscription content, access via your institution

Access options

Buy this article

  • Purchase on SpringerLink
  • Instant access to full article PDF
Buy now

Prices may be subject to local taxes which are calculated during checkout

Figure 1: A schematic view of a classical bulk n-channel MOSFET.
Figure 2: The drain current as a function of gate voltage in a MOSFET.
Figure 3: The evolution of transistor gate length (minimum feature size) and the density of transistors in microprocessors over time.
Figure 4: Illustration of short-channel effects.
Figure 5: Types of multigate MOSFET.
Figure 6: A multifingered (three-finger) silicon nanowire transistor.
Figure 7: Competition between the different electric fields for an elemental volume in the channel region.
Figure 8: Variation of the DIBL effect with channel length.

Similar content being viewed by others

References

  1. Armstrong, G. A., Davis, J. R. & Doyle A. Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation. IEEE Trans. Electron Devices 38, 328–336 (1991).

    Article  ADS  Google Scholar 

  2. Moselund, K. E. et al. Punch-through impact ionization MOSFET (PIMOS): from device principle to applications. Solid State Electron. 52, 1336–1344 (2008).

    Article  CAS  ADS  Google Scholar 

  3. Zhang, Q., Zhao, W. & Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27, 297–300 (2006).

    Article  CAS  ADS  Google Scholar 

  4. Afzalian, A., Colinge, J. P. & Flandre, D. Physics of gate modulated resonant tunneling (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current. Solid State Electron. 59, 50–61 (2011).

    Article  CAS  ADS  Google Scholar 

  5. Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).

    Article  CAS  ADS  Google Scholar 

  6. Moore, G. E. Cramming more components onto integrated circuits. Electronics 8, 114–117 (1965).

    Google Scholar 

  7. Dennard, R. H. et al. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J. Solid-State Circuits 9, 256–268 (1974).

    Article  ADS  Google Scholar 

  8. Skotnicki, T. & Boeuf, T. How can high-mobility channel materials boost or degrade performance in advanced CMOS. Symp. VLSI Technol. 153–154 (IEEE, 2010).

    Google Scholar 

  9. Engström, O. et al. in Nanoscale CMOS: Innovative Materials, Modeling and Characterization (ed. Balestra, F.) Ch. 2 (Wiley-ISTE, 2010).

    Google Scholar 

  10. Grove, A. S. Physics and Technology of Semiconductor Devices Ch. 11 (Wiley, 1967).

    Google Scholar 

  11. Colinge, J. P. Multiple-gate SOI MOSFETs. Solid State Electron. 48, 897–905 (2004). This technical review paper provides a detailed comparison of the efficiency of channel control by the gate with single-gate, double-gate, tri-gate and gate-all-around configurations, and it introduces the concept of natural length and shows its relationship to short-channel effects.

    Article  CAS  ADS  Google Scholar 

  12. Skotnicki, T. et al. Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans. Electron Devices 55, 96–130 (2008).

    Article  ADS  Google Scholar 

  13. Sekigawa, T. & Hayashi, Y. Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid State Electron. 27, 827–828 (1984).

    Article  ADS  Google Scholar 

  14. Hisamoto, D., Kaga, T., Kawamoto, Y. & Takeda, E. A fully depleted lean-channel transistor (DELTA): a novel vertical ultra thin SOI MOSFET. Tech. Digest IEEE Electron Devices Meet. 833–836 (IEEE, 1989). The DELTA transistor was the first multigate transistor, and dynamic random access memory cells based on DELTA devices were reported two years later.

    Google Scholar 

  15. Huang, X. et al. Sub 50-nm FinFET: PMOS. Tech. Digest IEEE Electron Devices Meet. 67–70 (IEEE, 1999).

    Google Scholar 

  16. Baie, X., Colinge, J. P., Bayot, V. & Grivei, E. Quantum-wire effects in thin and narrow SOI MOSFETs. IEEE Int. SOI Conf. Proc. 66–67 (IEEE, 1995).

    Google Scholar 

  17. Doyle, B. S. et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett. 24, 263–265 (2003).

    Article  CAS  ADS  Google Scholar 

  18. Park, J. T., Colinge, J. P. & Diaz, C. H. Pi-gate SOI MOSFET. IEEE Electron Device Lett. 22, 405–406 (2001).

    Article  ADS  Google Scholar 

  19. Yang, F. L. et al. 25 nm CMOS omega FETs. Tech. Digest IEEE Electron Devices Meet. 255–258 (IEEE, 2002).

    Book  Google Scholar 

  20. Colinge, J. P., Gao, M. H., Romano, A., Maes, H. & Claeys C. Silicon-on-insulator 'gate-all-around device'. Tech. Digest IEEE Electron Devices Meet. 595–598 (IEEE, 1990).

    Book  Google Scholar 

  21. Colinge, J. P. et al. Nanowire transistors without junctions. Nature Nanotechnol. 5, 225–229 (2010).

    Article  CAS  ADS  Google Scholar 

  22. Ansari, L., Feldman, B., Fagas, G., Colinge, J. P. & Greer, J. C. Simulation of junctionless Si nanowire transistors with 3 nm gate length. Appl. Phys. Lett. 97, 062105 (2010).

    Article  ADS  Google Scholar 

  23. Hofmann, F. et al. NVM based on FinFET device structures. Solid State Electron. 49, 1799–1804 (2005).

    Article  CAS  ADS  Google Scholar 

  24. Tang, X. et al. Self-aligned SOI nano flash memory device. Solid State Electron. 44, 2259–2264 (2000).

    Article  CAS  ADS  Google Scholar 

  25. Suk, S. D. et al. Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure. Symp. VLSI Technol. 142–143 (IEEE, 2009).

    Google Scholar 

  26. Park, J. T., Colinge, C. A. & Colinge, J. P. Comparison of gate structures for short-channel SOI MOSFETs. IEEE Int. SOI Conf. 115–116 (IEEE, 2001).

    Google Scholar 

  27. Kuhn, K. J. CMOS transistor scaling past 32nm and implications on variation. IEEE/SEMI Advanced Semicond. Manuf. Conf. 241–246 (IEEE, 2010).

    Google Scholar 

  28. Okano, K. et al. Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10nm fin width and 20nm gate length. Tech. Digest IEEE Electron Devices Meet. 725–728 (IEEE, 2005).

    Google Scholar 

  29. Cho, H. J. et al. Fin width scaling criteria of body-tied FinFET in sub-50 nm regime. Conf. Digest Device Res. Conf. 209–210 (IEEE, 2004).

    Google Scholar 

  30. Kanemura, T., Izumida, T., Aoki, N. & Kondo, M. Improvement of drive current in bulk-FinFET using full 3D process/device simulations. Int. Conf. Simulation Semicond. Processes Devices 131–134 (IEEE, 2006).

    Google Scholar 

  31. Cao, S., Chun, J. H., Salman, A. A., Beebe, S. G. & Dutton, R. W. Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology. Microelectron. Reliab. 51, 756–764 (2011).

    Article  CAS  Google Scholar 

  32. Thijs, S. et al. Advanced ESD power clamp design for SOI FinFET CMOS technology. Int. Conf. IC Design Technol. 43–46 (IEEE, 2010).

    Google Scholar 

  33. Subramanian, V. et al. Planar bulk MOSFETs versus FinFETs: an analog/RF perspective. IEEE Trans. Electron Devices 12, 3071–3079 (2006).

    Article  ADS  Google Scholar 

  34. Yan, R. H., Ourmazd, A. & Lee, K. F. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1704–1710 (1992).

    Article  CAS  ADS  Google Scholar 

  35. Lee, C. W. et al. Device design guidelines for nano-scale MuGFETs. Solid State Electron. 51, 505–510 (2007).

    Article  CAS  ADS  Google Scholar 

  36. Colinge, J. P. in FinFETs and Other Multi-Gate Transistors (ed. Colinge, J. P.) 1–48 (Springer, 2007).

    Google Scholar 

  37. Kavalieros, J. et al. Tri-gate transistor architecture with high-κ gate dielectrics, metal gates and strain engineering. Digest Tech. Papers Symp. VLSI Technol. 50–51 (IEEE, 2006).

    Google Scholar 

  38. Yeh, C.-C. et al. A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology. IEEE Electron Devices Meet. 772–775 (IEEE, 2011).

    Google Scholar 

  39. Joshi, R. V. et al. FinFET SRAM for high-performance low-power applications. Proc. 34th Eur. Solid-State Device Res. Conf. 69–72 (IEEE, 2004).

    Google Scholar 

  40. Basker, V. et al. A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch. Symp. VLSI Technol. 19–20 (IEEE, 2010).

    Google Scholar 

  41. Guillorn, M. A. et al. A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch. Symp. VLSI Technol. 64–65 (IEEE, 2011).

    Google Scholar 

  42. Wu, C. C. et al. High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme. IEEE Electron Devices Meet. 600–603 (IEEE, 2011).

    Google Scholar 

  43. ITRS International Technology Working Groups. ITRS 2010 update. International Road Map for Semiconductors 〈http://www.itrs.net/Links/2010ITRS/2010Update/ToPost/2010Tables_ORTC_ITRS.xls〉 (2010).

Download references

Acknowledgements

This work was supported by Science Foundation Ireland grants 05/IN/I888, 07/IN.1/I937 and 10/IN.1/I2992, the European project SQWIRE under Grant Agreement No. 257111 and the European Community (EC) Seventh Framework Program through the Network of Excellence Nano-TEC under Contract 257964. We thank N. Petkov and M. Schmidt for the electron microscopy images in Fig. 6.

Author information

Authors and Affiliations

  1. Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade, Cork, Ireland

    Isabelle Ferain, Cynthia A. Colinge & Jean-Pierre Colinge

Authors
  1. Isabelle Ferain
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Cynthia A. Colinge
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jean-Pierre Colinge
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jean-Pierre Colinge.

Ethics declarations

Competing interests

The authors declare no competing financial interests.

Additional information

Reprints and permissions information is available at http://www.nature.com/reprints.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ferain, I., Colinge, C. & Colinge, JP. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011). https://doi.org/10.1038/nature10676

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/nature10676

Search

Advanced search

Quick links

Nature Briefing AI and Robotics

Sign up for the Nature Briefing: AI and Robotics newsletter — what matters in AI and robotics research, free to your inbox weekly.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing: AI and Robotics