Article

Minimising buffer requirements of synchronous dataflow graphs with model checking

Authors:

Sander StuijkAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 819 - 824

https://doi.org/10.1145/1065579.1065796

Published: 13 June 2005 Publication History

Abstract

Signal processing and multimedia applications are often implemented on resource constrained embedded systems. It is therefore important to find implementations that use as little resources as possible. These applications are frequently specified as synchronous dataflow graphs. Communication between actors of these graphs requires storage capacity. In this paper, we present an exact method to determine the minimum storage capacity required to execute the graph using model-checking techniques. This can be done for different measures of storage capacity. The problem is known to be NP-complete and because of this, existing buffer minimisation techniques are heuristics and hence not exact. Modern model-checking tools are quite efficient and they have been successfully applied to scheduling-related problems. We study the feasibility of this approach with examples.

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Cited By

Menard CLohstroh MBateni SChorlian MDeng ADonovan PFournier CLin SSuchert FTanneberger TKim HCastrillon JLee E(2023)High-performance Deterministic Concurrency Using Lingua FrancaACM Transactions on Architecture and Code Optimization10.1145/361768720:4(1-29)Online publication date: 26-Oct-2023
https://dl.acm.org/doi/10.1145/3617687
Fradet PGirault AHonorat AEgger BLee D(2023)Sequential Scheduling of Dataflow Graphs for Memory Peak MinimizationProceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3589610.3596280(76-86)Online publication date: 13-Jun-2023
https://dl.acm.org/doi/10.1145/3589610.3596280
Xu JMurphy ECortadella JJosipovic LIenne PZhang Z(2023)Eliminating Excessive Dynamism of Dataflow Circuits Using Model CheckingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573196(27-37)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573196
Show More Cited By

Index Terms

Minimising buffer requirements of synchronous dataflow graphs with model checking
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems

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Published In

cover image ACM Conferences

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Copyright © 2005 ACM.

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Published: 13 June 2005

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June 13 - 17, 2005

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Menard CLohstroh MBateni SChorlian MDeng ADonovan PFournier CLin SSuchert FTanneberger TKim HCastrillon JLee E(2023)High-performance Deterministic Concurrency Using Lingua FrancaACM Transactions on Architecture and Code Optimization10.1145/361768720:4(1-29)Online publication date: 26-Oct-2023
https://dl.acm.org/doi/10.1145/3617687
Fradet PGirault AHonorat AEgger BLee D(2023)Sequential Scheduling of Dataflow Graphs for Memory Peak MinimizationProceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3589610.3596280(76-86)Online publication date: 13-Jun-2023
https://dl.acm.org/doi/10.1145/3589610.3596280
Xu JMurphy ECortadella JJosipovic LIenne PZhang Z(2023)Eliminating Excessive Dynamism of Dataflow Circuits Using Model CheckingProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573196(27-37)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573196
Josipovic LGuerrieri AIenne P(2022)From C/C++ Code to High-Performance Dataflow CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310557441:7(2142-2155)Online publication date: Jul-2022
https://doi.org/10.1109/TCAD.2021.3105574
Roumage GAzaiez SLouise S(2022)A survey of main dataflow MoCCs for CPS design and verification2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC57363.2022.00010(1-9)Online publication date: Dec-2022
https://doi.org/10.1109/MCSoC57363.2022.00010
Song SVarshika MDas AKandasamy N(2021)A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643500(1-9)Online publication date: 1-Nov-2021
https://doi.org/10.1109/ICCAD51958.2021.9643500
Dubrulle PKosmatov NGaston CLapitre A(2020)PolyGraph: a data flow model with frequency arithmeticInternational Journal on Software Tools for Technology Transfer10.1007/s10009-020-00586-9Online publication date: 2-Sep-2020
https://doi.org/10.1007/s10009-020-00586-9
Edwards STownsend RBarker MKim M(2019)Compositional Dataflow CircuitsACM Transactions on Embedded Computing Systems10.1145/327428018:1(1-27)Online publication date: 25-Jan-2019
https://dl.acm.org/doi/10.1145/3274280
Dubrulle PGaston CKosmatov NLapitre ALouise S(2019)A Data Flow Model with Frequency ArithmeticFundamental Approaches to Software Engineering10.1007/978-3-030-16722-6_22(369-385)Online publication date: 4-Apr-2019
https://doi.org/10.1007/978-3-030-16722-6_22
Wiik JErsfolk JWaldén MHu KZhan N(2018)A contract-based approach to scheduling and verification of dynamic dataflow networksProceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343872.3343882(78-87)Online publication date: 15-Oct-2018
https://dl.acm.org/doi/10.5555/3343872.3343882
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