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LimitLESS directories: A scalable cache coherence scheme

Authors:

David Chaiken,

John Kubiatowicz,

Anant AgarwalAuthors Info & Claims

ACM SIGPLAN Notices, Volume 26, Issue 4

Pages 224 - 234

https://doi.org/10.1145/106973.106995

Published: 01 April 1991 Publication History

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Cited By

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Larus JRajwar RLarus JRajwar R(2022)Hardware-Supported Transactional MemoryTransactional Memory10.1007/978-3-031-01719-3_4(131-205)Online publication date: 17-Oct-2022
https://doi.org/10.1007/978-3-031-01719-3_4
Liu PFang LHuang M(2014)DEAM: Decoupled, Expressive, Area-Efficient Metadata CacheJournal of Computer Science and Technology10.1007/s11390-014-1459-029:4(679-691)Online publication date: 4-Jul-2014
https://doi.org/10.1007/s11390-014-1459-0
Ros AAcacio MGarcía J(2010)A scalable organization for distributed directoriesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2009.11.00656:2-3(77-87)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1016/j.sysarc.2009.11.006
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LimitLESS directories: A scalable cache coherence scheme

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LIMITLESS DIRECTORIES: A SCALABLE CACHE COHERENCE SCHEME
Multi-grain coherence directories
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Conventional directory coherence operates at the finest granularity possible, that of a cache block. While simple, this organization fails to exploit frequent application behavior: at any given point in time, large, continuous chunks of memory are often ...
Cache Coherence Directories for Scalable Multiprocessors

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Information

Published In

ACM SIGPLAN Notices Volume 26, Issue 4

Special issue of a journal and a proceedings

Apr. 1991

305 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/106973

Editor:
David A. Patterson
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
April 1991
320 pages
ISBN:0897913809
DOI:10.1145/106972
Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1991

Published in SIGPLAN Volume 26, Issue 4

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Cited By

View all

Larus JRajwar RLarus JRajwar R(2022)Hardware-Supported Transactional MemoryTransactional Memory10.1007/978-3-031-01719-3_4(131-205)Online publication date: 17-Oct-2022
https://doi.org/10.1007/978-3-031-01719-3_4
Liu PFang LHuang M(2014)DEAM: Decoupled, Expressive, Area-Efficient Metadata CacheJournal of Computer Science and Technology10.1007/s11390-014-1459-029:4(679-691)Online publication date: 4-Jul-2014
https://doi.org/10.1007/s11390-014-1459-0
Ros AAcacio MGarcía J(2010)A scalable organization for distributed directoriesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2009.11.00656:2-3(77-87)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1016/j.sysarc.2009.11.006
Ros AAcacio MGarcía J(2009)Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPsProceedings of the 8th International Symposium on Advanced Parallel Processing Technologies10.1007/978-3-642-03644-6_2(11-27)Online publication date: 21-Aug-2009
https://dl.acm.org/doi/10.1007/978-3-642-03644-6_2
Larus JRajwar R(2006)Transactional MemorySynthesis Lectures on Computer Architecture10.2200/S00070ED1V01Y200611CAC0021:1(1-226)Online publication date: Jan-2006
https://doi.org/10.2200/S00070ED1V01Y200611CAC002
Frank SBurkhardt HRothnie J(1993)The KSR1: High Performance and Ease of Programming, No Longer an OxymoronSupercomputer ’9310.1007/978-3-642-78348-7_7(53-70)Online publication date: 1993
https://doi.org/10.1007/978-3-642-78348-7_7
Franques AKokolis AAbadal SFernando VMisailovic STorrellas J(2021)WiDir: A Wireless-Enabled Directory Cache Coherence Protocol2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00034(304-317)Online publication date: Mar-2021
https://doi.org/10.1109/HPCA51647.2021.00034
Srivatsa AMansour MRheindt SGabriel DWild THerkersdorf A(2021)DynaCo: Dynamic Coherence Management for Tiled Manycore ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00688-6Online publication date: 3-Jan-2021
https://doi.org/10.1007/s10766-020-00688-6
Yan MWen JFletcher CTorrellas JManne SHunter HAltman E(2019)SecDirProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3326635(332-345)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3326635
Srivatsa ARheindt SGabriel DWild THerkersdorf A(2019)CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore ArchitecturesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_2(18-33)Online publication date: 8-Aug-2019
https://doi.org/10.1007/978-3-030-27562-4_2
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