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A multicast inter-task communication protocol for embedded multiprocessor systems

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Wido KruijtzerAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 267 - 272

https://doi.org/10.1145/1084834.1084901

Published: 19 September 2005 Publication History

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Abstract

Recently, a new programming model and platform interface for MPSoC design and integration called TTL (Task Transaction Level) has been developed and advocated as a standard. In this paper, a specific implementation of the TTL interface named ITCP (Inter-Task Communication Protocol) is presented. ITCP is well suited for both hardware and software implementations and supports features such as multitasking and multicast communication. A configurable SystemC model of the ITCP protocol and its integration in a system-level design methodology is disclosed in this work. Moreover, details of a multi-task ITCP software shell implementation for an ARM9 with eCos RTOS are also given in the paper.

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Cited By

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Xu JGu HZhang WLiu W(2012)FONoC: A Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-ChipIntegrated Optical Interconnect Architectures for Embedded Systems10.1007/978-1-4419-6193-8_4(137-152)Online publication date: 27-Sep-2012
https://doi.org/10.1007/978-1-4419-6193-8_4
Gu HXu JZhang WBenini LDe Micheli GAl-Hashimi BMueller W(2009)A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874625(3-8)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874625
Huaxi Gu Jiang Xu Wei Zhang (2009)A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090624(3-8)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090624
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A multicast inter-task communication protocol for embedded multiprocessor systems

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Published In

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2005

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CODES/ISSS05

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

NJ, Jersey City, USA

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CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

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Xu JGu HZhang WLiu W(2012)FONoC: A Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-ChipIntegrated Optical Interconnect Architectures for Embedded Systems10.1007/978-1-4419-6193-8_4(137-152)Online publication date: 27-Sep-2012
https://doi.org/10.1007/978-1-4419-6193-8_4
Gu HXu JZhang WBenini LDe Micheli GAl-Hashimi BMueller W(2009)A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chipProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874625(3-8)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874625
Huaxi Gu Jiang Xu Wei Zhang (2009)A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090624(3-8)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090624
Jia ZBautista TNúnez AGuerra CHernández M(2008)Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoCProceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2008.33(193-198)Online publication date: 3-Dec-2008
https://dl.acm.org/doi/10.1109/ReConFig.2008.33
García LCallico GBarreto DReyes VBautista TNunez A(2007)Towards a configurable SoC MPEG-4 advanced simple profile decoderIET Computers & Digital Techniques10.1049/iet-cdt:200600541:5(451)Online publication date: 2007
https://doi.org/10.1049/iet-cdt:20060054
Reyes VKruijtzer WBautista TAlkadi GNúñez AGielen G(2006)A unified system-level modeling and simulation environment for MPSoC designProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131608(474-479)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131608

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