Article

Iterational retiming: maximize iteration-level parallelism for nested loops

Authors:

Chun Xue,

Zili Shao,

Meilin Liu,

Edwin H.-M. ShaAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 309 - 314

https://doi.org/10.1145/1084834.1084910

Published: 19 September 2005 Publication History

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Abstract

Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP)applications.It is important to study effective and efficient transformation techniques to increase parallelism for nested loops.In this paper, we propose a novel technique,iterational retiming,that can satisfy any given timing constraint by achieving full parallelism for iterations in a partition. Theorems and efficient algorithms are proposed for iterational retiming. The experimental results show that iterational retiming is a promising technique for parallel embedded systems.It can achieve 87% improvement over software pipelining and 88%improvement over loop unfolding on average.

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Cited By

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Wang YLi KLi K(2015)Minimizing write operation for multi-dimensional DSP applications via a two-level partition technique with complete memory latency hidingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.02.00161:2(112-126)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.02.001
Elloumi YAkil MBedoui M(2013)Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop StripingProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.132(462-466)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.132
Xue CHu JShao ZSha E(2010)Iterational retiming with partitioningACM Transactions on Embedded Computing Systems10.1145/1698772.16987809:3(1-26)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698780
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Index Terms

Iterational retiming: maximize iteration-level parallelism for nested loops
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2005

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CODES/ISSS05

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

NJ, Jersey City, USA

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CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

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Wang YLi KLi K(2015)Minimizing write operation for multi-dimensional DSP applications via a two-level partition technique with complete memory latency hidingJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.02.00161:2(112-126)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.02.001
Elloumi YAkil MBedoui M(2013)Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop StripingProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.132(462-466)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.132
Xue CHu JShao ZSha E(2010)Iterational retiming with partitioningACM Transactions on Embedded Computing Systems10.1145/1698772.16987809:3(1-26)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698780
Liu DShao ZWang MGuo MXue JHenkel JParameswaran S(2009)Optimal loop parallelization for maximizing iteration-level parallelismProceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1629395.1629407(67-76)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629395.1629407
Xue CShao ZLiu MQiu MSha E(2006)Loop Scheduling with Complete Memory Latency Hiding on Multi-core ArchitectureProceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 110.1109/ICPADS.2006.58(375-382)Online publication date: 12-Jul-2006
https://dl.acm.org/doi/10.1109/ICPADS.2006.58

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Achieving Full Parallelism Using Multidimensional Retiming

Optimizing nested loops with iterational and instructional retiming

Optimizing parallelism for nested loops with iterational and instructional retiming