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Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

Published: 24 January 2006 Publication History

Abstract

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

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Cited By

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  • (2012)Optimizing explicit data transfers for data parallel applications on the cell architectureACM Transactions on Architecture and Code Optimization10.1145/2086696.20867168:4(1-20)Online publication date: 26-Jan-2012
  • (2011)Analysis of integrated circuits thermal dynamics with point heating timeMicroelectronics Journal10.1016/j.mejo.2010.09.01142:1(1-11)Online publication date: 1-Jan-2011
  • (2008)Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policiesACM Transactions on Embedded Computing Systems10.1145/1331331.13313337:2(1-19)Online publication date: 29-Jan-2008
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  1. Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

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          Published In

          cover image ACM Conferences
          ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
          January 2006
          998 pages
          ISBN:0780394518

          Sponsors

          • IEEE Circuits and Systems Society
          • SIGDA: ACM Special Interest Group on Design Automation
          • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
          • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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          IEEE Press

          Publication History

          Published: 24 January 2006

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          Author Tags

          1. 64-bit Power Architecture
          2. CELL Processor
          3. Linux
          4. SOC
          5. SOI
          6. clock distribution
          7. correct-by-construction
          8. design dependency solution
          9. design environment
          10. design hierarchy
          11. digital thermal sensor
          12. flexible IO
          13. hardware content protection
          14. high-performance latch
          15. linear sensor
          16. local clock buffer
          17. modularity
          18. multi-core
          19. multi-operating system
          20. multi-threading
          21. power management
          22. re-use
          23. real-time system
          24. synergistic processor
          25. thermal management
          26. virtualization technology

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          Cited By

          View all
          • (2012)Optimizing explicit data transfers for data parallel applications on the cell architectureACM Transactions on Architecture and Code Optimization10.1145/2086696.20867168:4(1-20)Online publication date: 26-Jan-2012
          • (2011)Analysis of integrated circuits thermal dynamics with point heating timeMicroelectronics Journal10.1016/j.mejo.2010.09.01142:1(1-11)Online publication date: 1-Jan-2011
          • (2008)Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policiesACM Transactions on Embedded Computing Systems10.1145/1331331.13313337:2(1-19)Online publication date: 29-Jan-2008
          • (2008)Interrupt modeling for efficient high-level scheduler design space explorationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767613:1(1-22)Online publication date: 6-Feb-2008
          • (2008)Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal TransformsProceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2008.70(103-108)Online publication date: 3-Dec-2008
          • (2006)Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policiesProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176261(16-21)Online publication date: 22-Oct-2006

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