Article

Enhanced symbolic simulation for efficient verification of embedded array systems

Authors:

Kwang-Ting Cheng,

Magdy S. AbadirAuthors Info & Claims

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Pages 302 - 307

https://doi.org/10.1145/1119772.1119830

Published: 21 January 2003 Publication History

Abstract

In the past, Symbolic Trajectory Evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and data-path domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.

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Cited By

Cherupalli HDuwe HYe WKumar RSartori J(2017)Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power ProcessorsACM Transactions on Computer Systems10.1145/314805235:3(1-33)Online publication date: 26-Dec-2017
https://dl.acm.org/doi/10.1145/3148052
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsACM SIGARCH Computer Architecture News10.1145/3140659.308024745:2(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080247
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080247(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080247
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cover image ACM Conferences

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

January 2003

865 pages

ISBN:0780376609

DOI:10.1145/1119772

General Chair:
Hiroto Yasuura

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IPSJ: Information Processing Society of Japan
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SIGDA: ACM Special Interest Group on Design Automation
IEICE: Institute of Electronics, Information and Communication Engineers

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2003

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Cherupalli HDuwe HYe WKumar RSartori J(2017)Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power ProcessorsACM Transactions on Computer Systems10.1145/314805235:3(1-33)Online publication date: 26-Dec-2017
https://dl.acm.org/doi/10.1145/3148052
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsACM SIGARCH Computer Architecture News10.1145/3140659.308024745:2(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080247
Cherupalli HDuwe HYe WKumar RSartori J(2017)Bespoke Processors for Applications with Ultra-low Area and Power ConstraintsProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080247(41-54)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080247
Chen XHsiao M(2007)An overlapping scan architecture for reducing both test time and test power by pipelining fault detectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89365715:4(404-412)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.893657
Feng TWang LCheng KLin A(2004)Improved Symoblic Simulation by Dynamic Funtional Space PartitioningProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969004Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969004
Feng TWang LCheng KImai M(2004)Improved symbolic simulation by functional-space decompositionProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015263(634-639)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015263
Tao Feng Wang LKwang-Ting Cheng (2004)Improved symbolic simulation by functional-space decompositionASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337669(634-639)Online publication date: 2004
https://doi.org/10.1109/ASPDAC.2004.1337669

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