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High-performance packet classification algorithm for many-core and multithreaded network processor

Published: 22 October 2006 Publication History

Abstract

Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based classification algorithms have been proposed. However, classifying at 10Gbps speed or higher is a challenging problem and it is still one of the performance bottlenecks in core routers. In general, classification algorithms face the same challenge of balancing between high classification speed and low memory requirements. This paper proposes a modified Recursive Flow Classification (RFC) algorithm, Bitmap-RFC, which significantly reduces the memory requirements of RFC by applying a bitmap compression technique. To speed up classifying speed, we experiment on exploiting the architectural features of a many-core and multithreaded architecture from algorithm design to algorithm implementation. As a result, Bitmap-RFC strikes a good balance between speed and space. It can not only keep high classification speed but also reduce memory space significantly.This paper investigates the main NPU software design aspects that have dramatic performance impacts on any NPU-based implementations: memory space reduction, instruction selection, data allocation, task partitioning, and latency hiding. We experiment with an architecture-aware design principle to guarantee the high performance of the classification algorithm on an NPU implementation. The experimental results show that the Bitmap-RFC algorithm achieves 10Gbps speed or higher and has a good scalability on Intel IXP2800 NP.

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  • (2017)Noff: A Novel Extendible Parallel Library for High-Performance Network Traffic Monitoring2017 24th Asia-Pacific Software Engineering Conference (APSEC)10.1109/APSEC.2017.19(130-139)Online publication date: Dec-2017
  • (2016)A customized and reconfigurable VLIW-based packet classifier on ρ-VEXJournal of High Speed Networks10.3233/JHS-16054122:3(177-192)Online publication date: 2-Jun-2016
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cover image ACM Conferences
CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
October 2006
448 pages
ISBN:1595935436
DOI:10.1145/1176760
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 October 2006

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Author Tags

  1. architecture
  2. embedded system design
  3. multithreading
  4. network processor
  5. packet classification
  6. thread-level parallelism

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ESWEEK06
ESWEEK06: Second Embedded Systems Week 2006
October 22 - 25, 2006
Seoul, Korea

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

View all
  • (2017)HyPaFilter+IEEE/ACM Transactions on Networking10.1109/TNET.2017.274969925:6(3655-3669)Online publication date: 1-Dec-2017
  • (2017)Noff: A Novel Extendible Parallel Library for High-Performance Network Traffic Monitoring2017 24th Asia-Pacific Software Engineering Conference (APSEC)10.1109/APSEC.2017.19(130-139)Online publication date: Dec-2017
  • (2016)A customized and reconfigurable VLIW-based packet classifier on ρ-VEXJournal of High Speed Networks10.3233/JHS-16054122:3(177-192)Online publication date: 2-Jun-2016
  • (2016)HyPaFilterProceedings of the 2016 Symposium on Architectures for Networking and Communications Systems10.1145/2881025.2881033(25-36)Online publication date: 17-Mar-2016
  • (2016)LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet ClassificationIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.25286386:1(73-86)Online publication date: Mar-2016
  • (2015)Packet Classification on Multi-core PlatformsHandbook on Data Centers10.1007/978-1-4939-2092-1_13(425-447)Online publication date: 17-Mar-2015
  • (2013)Multi-core Implementation of Decomposition-Based Packet Classification AlgorithmsProceedings of the 12th International Conference on Parallel Computing Technologies - Volume 797910.1007/978-3-642-39958-9_9(105-119)Online publication date: 30-Sep-2013
  • (2012)Approximate Packet Classification and Stateful Rule DFA for Cloud Intrusion DetectionProceedings of the 2012 International Conference on Computing, Measurement, Control and Sensor Network10.1109/CMCSN.2012.57(229-232)Online publication date: 7-Jul-2012
  • (2010)Workload characterization supporting the development of domain-specific compiler optimizations using decision trees for data miningProceedings of the 13th International Workshop on Software & Compilers for Embedded Systems10.1145/1811212.1811219(1-10)Online publication date: 28-Jun-2010
  • (2009)A Timesaving Recursive Flow Packet Classification AlgorithmProceedings of the 2009 International Conference on Networks Security, Wireless Communications and Trusted Computing - Volume 0210.1109/NSWCTC.2009.245(442-445)Online publication date: 25-Apr-2009
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