Article

Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor

Authors:

David SnuijfAuthors Info & Claims

SCOPES '07: Proceedingsof the 10th international workshop on Software & compilers for embedded systems

Pages 23 - 30

https://doi.org/10.1145/1269843.1269847

Published: 20 April 2007 Publication History

Abstract

When studying the IXP Network processor architecture from Intel, we found quite some interesting aspects that make the IXP attractive for stream-based applications. The architecture is highly optimized for streaming data, albeit in the form of internet packets. Furthermore, the architecture has Gigabit Ethernet connectors for handling incoming and outgoing traffic and can process this data at real-time using dedicated microengines. In this paper, we try to answer three questions; 1) Can we use the IXP architecture for stream-based applications? 2) can we map applications written as a KPN onto an IXP? 3) can we integrate the generation of KPNs using the Compaan compiler with a tool flow that maps the KPN to an IXP, thereby make the programming of IXP much simpler? As will be shown, all three steps can be performed and we show that we can map automatically two non-internet stream-based applications (QR and DWT) onto the IXP.

References

[1]

Matthew Adiletta, Mark Rosenbluth, and Debra Bernstein. The next generation of intel ixp network processors. Intel Technology Journal, 06(03), 15 aug 2002.

[2]

Herbert Bos and Kaiming Huang. On the feasibility of using network processors for dna queries. In Proceedings of the Third Workshop on Network Processors & Applications (NP-3), pages 183 -- 195, 2004.

[3]

Lal George and Matthias Blume. Taming the ixp network processor. In PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation, pages 26--37, New York, NY, USA, 2003. ACM Press.

Digital Library

[4]

C. A. R. Hoare. Communicating sequential processes. Commun. ACM, 21(8):666--677, 1978.

Digital Library

[5]

G. Kahn. The semantics of a simple language for parallel programming. In J. L. Rosenfeld, editor, Information processing, pages 471--475, Stockholm, Sweden, Aug 1974. North Holland, Amsterdam.

[6]

Bart Kienhuis, Edwin Rijpkema, and Ed F. Deprettere. Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures. In Proc. 8th International Workshop on Hardware/Software Codesign (CODES'2000), San Diego, CA, USA, May 3--5 2000.

Digital Library

[7]

Long Li, Bo Huang, Jinquan Dai, and Luddy Harrison. Automatic multithreading and multiprocessing of c programs for ixp. In PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, pages 132--141, New York, NY, USA, 2005. ACM Press.

Digital Library

[8]

D. Pham et al. The design and implementation of a first-generation cell processor. In In ISSCC Digest of Technical Papers, pages p. 184--5, 2005.

[9]

Hristo Nikolov, Todor Stefanov, and Ed Deprettere. Multiprocessor system design with ESPAM. In CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, pages 211--216, New York, NY, USA, 2006. ACM Press.

Digital Library

[10]

Niraj Shah, William Plishker, Kaushik Ravindran, and Kurt Keutzer. Np-click: A productive software development approach for network processors. IEEE Micro, 24(5):45--54, 2004.

Digital Library

[11]

Todor Stefanov, Bart Kienhuis, and Ed Deprettere. Algorithmic transformation techniques for efficient exploration of alternative application instances. In CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign, pages 7--12, New York, NY, USA, 2002. ACM Press.

Digital Library

[12]

Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, and Ed Deprettere. System design using kahn process networks: The compaan/laura approach. In Proceedings of DATE2004, Paris, France, Feb 16 -- 20 2004.

Digital Library

[13]

Paul Stravers and Jan Hoogerbrugge. Homogeneous multiprocessing and the future of silicon design paradigms. In In Prce. International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA 2001), April 2001.

[14]

NST: Network Speed Technologies. http://www.network-speed.com.

[15]

Alexandru Turjan, Bart Kienhuis, and Ed Deprettere. Translating affine nested loops to Process Networks. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Washington D.C., September 23--25 2004.

Digital Library

[16]

Ben Wun, Jeremy Buhler, and Patrick Crowley. Exploiting coarse-grained parallelism to accelerate protein motif finding with a network processor. In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05), pages 173 -- 184, 2005.

Digital Library

[17]

Claudiu Zissulescu. Synthesizing Process Networks to VHDL. PhD thesis, LIACS, Leiden University, The Netherlands, 2007.

[18]

Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, and Ed Deprettere. LAURA: Leiden Architecture Research and Exploration Tool. In Proc. 13th Int. Conference on Field Programmable Logic and Applications (FPL'03), 2003.

Cited By

Odendahl MCastrillon JVolevach VLeupers RAscheid G(2013)Split-cost communication model for improved MPSoC application mapping2013 International Symposium on System on Chip (SoC)10.1109/ISSoC.2013.6675280(1-8)Online publication date: Oct-2013
https://doi.org/10.1109/ISSoC.2013.6675280
Castrillon JTretter ALeupers RAscheid GGroeneveld PSciuto DHassoun S(2012)Communication-aware mapping of KPN applications onto heterogeneous MPSoCsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228597(1266-1271)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228597
Sheng WWiebe AStulova ALeupers RKienhuis BWalters JAscheid G(2012)FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 PlatformProceedings of the 2012 IEEE 6th International Symposium on Embedded Multicore SoCs10.1109/MCSoC.2012.15(51-58)Online publication date: 20-Sep-2012
https://dl.acm.org/doi/10.1109/MCSoC.2012.15
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cover image ACM Conferences

SCOPES '07: Proceedingsof the 10th international workshop on Software & compilers for embedded systems

April 2007

127 pages

ISBN:9781450378345

DOI:10.1145/1269843

Editors:
Heiko Falk
University of Dortmund, Germany
,
Peter Marwedel
University of Dortmund, Germany

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 20 April 2007

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Cited By

Odendahl MCastrillon JVolevach VLeupers RAscheid G(2013)Split-cost communication model for improved MPSoC application mapping2013 International Symposium on System on Chip (SoC)10.1109/ISSoC.2013.6675280(1-8)Online publication date: Oct-2013
https://doi.org/10.1109/ISSoC.2013.6675280
Castrillon JTretter ALeupers RAscheid GGroeneveld PSciuto DHassoun S(2012)Communication-aware mapping of KPN applications onto heterogeneous MPSoCsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228597(1266-1271)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228597
Sheng WWiebe AStulova ALeupers RKienhuis BWalters JAscheid G(2012)FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 PlatformProceedings of the 2012 IEEE 6th International Symposium on Embedded Multicore SoCs10.1109/MCSoC.2012.15(51-58)Online publication date: 20-Sep-2012
https://dl.acm.org/doi/10.1109/MCSoC.2012.15
Abel FHagleitner CVerplanken F(2012)Rx Stack Accelerator for 10 GbE Integrated NICProceedings of the 2012 IEEE 20th Annual Symposium on High-Performance Interconnects10.1109/HOTI.2012.18(17-24)Online publication date: 22-Aug-2012
https://dl.acm.org/doi/10.1109/HOTI.2012.18
Javaid HHe XIgnjatovic AParameswaran SGivargis TDonlin A(2010)Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applicationsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1878978(75-84)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878961.1878978

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