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Understanding cache hierarchy interactions with a program-driven simulator

Authors:

Leticia Pascual,

Alejandro Torrentí,

Julio Sahuquillo,

José FlichAuthors Info & Claims

WCAE '07: Proceedings of the 2007 workshop on Computer architecture education

Pages 30 - 35

https://doi.org/10.1145/1275633.1275639

Published: 09 June 2007 Publication History

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Abstract

The increasing importance of the cache hierarchy in almost all digital systems governed by a microprocessor is demanding an appropriate set of tools to teach the interactions between caches. Students in computer organization/architecture courses face the problem of understanding how caches interact in a hierarchical organization. As caches grow in size and complexity, designing a tool to explore the different parameter interactions becomes challenging. Also, focusing only on the significant information (accessed lines and events) at different cache levels is required.

In this paper we present SpimVista, a tool developed on top of PC-Spim simulator, that simulates any MIPS code on a system with different cache hierarchy configurations. Each cache memory can be configured independently.

SpimVista is aimed at being used by undergraduate students, and the graphical interface has been designed addressed to ease the learning process. In particular, the tool offers an intuitive and easy interface that allows the student to focus on particular and interesting events as the program instructions are executed step-by-step. Also, students can perform interesting exercises where both the code and the impact of cache organization parameters on performance are analyzed globally.

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Lioris TDimitroulakos GMasselos K(2018)An early memory hierarchy evaluation simulator for multimedia applicationsMicroprocessors & Microsystems10.1016/j.micpro.2013.10.00638:1(31-41)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2013.10.006
Roy GGhosh DMandal C(2017)COLDVL: a virtual laboratory tool with novel features to support learning in logic design and computer organisationJournal of Computers in Education10.1007/s40692-017-0091-84:4(461-490)Online publication date: 29-Aug-2017
https://doi.org/10.1007/s40692-017-0091-8
Lioris TDimitroulakos GMasselos K(2010)XMSIMProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.106(375-380)Online publication date: 5-Jul-2010
https://dl.acm.org/doi/10.1109/ISVLSI.2010.106

Index Terms

Understanding cache hierarchy interactions with a program-driven simulator
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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WCAE '07: Proceedings of the 2007 workshop on Computer architecture education

June 2007

76 pages

ISBN:9781595937971

DOI:10.1145/1275633

Conference Chair:
Edward F. Gehringer
North Carolina State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 June 2007

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Lioris TDimitroulakos GMasselos K(2018)An early memory hierarchy evaluation simulator for multimedia applicationsMicroprocessors & Microsystems10.1016/j.micpro.2013.10.00638:1(31-41)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2013.10.006
Roy GGhosh DMandal C(2017)COLDVL: a virtual laboratory tool with novel features to support learning in logic design and computer organisationJournal of Computers in Education10.1007/s40692-017-0091-84:4(461-490)Online publication date: 29-Aug-2017
https://doi.org/10.1007/s40692-017-0091-8
Lioris TDimitroulakos GMasselos K(2010)XMSIMProceedings of the 2010 IEEE Annual Symposium on VLSI10.1109/ISVLSI.2010.106(375-380)Online publication date: 5-Jul-2010
https://dl.acm.org/doi/10.1109/ISVLSI.2010.106

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Tag-Split Cache for Efficient GPGPU Cache Utilization

Criticality aware tiered cache hierarchy: a fundamental relook at multi-level cache hierarchies

Write buffer design for cache-coherent shared-memory multiprocessors

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Tag-Split Cache for Efficient GPGPU Cache Utilization

Criticality aware tiered cache hierarchy: a fundamental relook at multi-level cache hierarchies

Write buffer design for cache-coherent shared-memory multiprocessors

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