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Incremental tree height reduction for high level synthesis

Authors:

Alexandru Nicolau,

Roni PotasmannAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 770 - 774

https://doi.org/10.1145/127601.127767

Published: 01 June 1991 Publication History

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Cited By

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Gao XWickerson JConstantinides GChen DGreene J(2016)Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level SynthesisProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847282(234-243)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847282
Winter VHussain S(2015)Verilog Synthesis in the Higher-Order Transformation Framework of TLProceedings of the 2015 IEEE 16th International Symposium on High Assurance Systems Engineering10.1109/HASE.2015.13(26-35)Online publication date: 8-Jan-2015
https://dl.acm.org/doi/10.1109/HASE.2015.13
Abboud FBen-Asher YShajrawi YStein E(2012)Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic OperationsInternational Journal of Parallel Programming10.1007/s10766-012-0196-740:5(488-513)Online publication date: 10-May-2012
https://doi.org/10.1007/s10766-012-0196-7
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Incremental tree height reduction for high level synthesis

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The height of a random binary search tree

Let H_n be the height of a random binary search tree on n nodes. We show that there exist constants α = 4.311… and β = 1.953… such that E(H_n) = αln n − βln ln n + O(1), We also show that Var(H_n) = O(1).

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DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Gao XWickerson JConstantinides GChen DGreene J(2016)Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level SynthesisProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847282(234-243)Online publication date: 21-Feb-2016
Winter VHussain S(2015)Verilog Synthesis in the Higher-Order Transformation Framework of TLProceedings of the 2015 IEEE 16th International Symposium on High Assurance Systems Engineering10.1109/HASE.2015.13(26-35)Online publication date: 8-Jan-2015
Abboud FBen-Asher YShajrawi YStein E(2012)Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic OperationsInternational Journal of Parallel Programming10.1007/s10766-012-0196-740:5(488-513)Online publication date: 10-May-2012
Gopalakrishnan SKalla P(2010)Algebraic Techniques to Enhance Common Sub-expression Extraction for Polynomial System SynthesisAdvanced Techniques in Logic Synthesis, Optimizations and Applications10.1007/978-1-4419-7518-8_14(251-266)Online publication date: 11-Nov-2010
Gopalakrishnan SKalla PBenini LDe Micheli GAl-Hashimi BMueller W(2009)Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874969(1452-1457)Online publication date: 20-Apr-2009
Zhu JDutt N(2009)Electronic system-level design and high-level synthesisElectronic Design Automation10.1016/B978-0-12-374364-0.50012-6(235-297)Online publication date: 2009
(2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
Hosangadi AFallah FKastner R(2007)Algebraic Methods for Optimizing Constant Multiplications in Linear SystemsJournal of VLSI Signal Processing Systems10.1007/s11265-007-0137-749:1(31-50)Online publication date: 1-Oct-2007
(2007)SoftwaresyntheseDigitale Hardware/Software-Systeme10.1007/978-3-540-46824-0_7(315-425)Online publication date: 2007
Hosangadi AFallah FKastner RGielen G(2006)Optimizing high speed arithmetic circuits using three-term extractionProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131838(1294-1299)Online publication date: 6-Mar-2006
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Constructing a minimum height elimination tree of a tree in linear time

On the Height of Multidimensional Height-Balanced Trees

The height of a random binary search tree

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Constructing a minimum height elimination tree of a tree in linear time

On the Height of Multidimensional Height-Balanced Trees

The height of a random binary search tree

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