Article

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

Authors:

Jaydeep P. Kulkarni,

Kaushik RoyAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 171 - 176

https://doi.org/10.1145/1283780.1283818

Published: 27 August 2007 Publication History

Abstract

We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175mV) VDD with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160mV in 0.13μm CMOS technology.

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Cited By

Sharma AKahol VSachdeva A(2024)Design of a Power-Efficient Static Random Access Memory Cell with Enhanced Stability for Internet of Things Applications2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT)10.1109/CSNT60213.2024.10546008(440-446)Online publication date: 6-Apr-2024
https://doi.org/10.1109/CSNT60213.2024.10546008
Ganesh CNoorbasha F(2023)Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM CellActive and Passive Electronic Components10.1155/2023/33715992023(1-17)Online publication date: 30-Jun-2023
https://doi.org/10.1155/2023/3371599
Saranga BGupta LSachdeva ASharma T(2023)Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT)10.1109/CSNT57126.2023.10134659(15-20)Online publication date: 8-Apr-2023
https://doi.org/10.1109/CSNT57126.2023.10134659
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Index Terms

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 27 August 2007

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ISLPED07

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Citations

Cited By

Sharma AKahol VSachdeva A(2024)Design of a Power-Efficient Static Random Access Memory Cell with Enhanced Stability for Internet of Things Applications2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT)10.1109/CSNT60213.2024.10546008(440-446)Online publication date: 6-Apr-2024
https://doi.org/10.1109/CSNT60213.2024.10546008
Ganesh CNoorbasha F(2023)Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM CellActive and Passive Electronic Components10.1155/2023/33715992023(1-17)Online publication date: 30-Jun-2023
https://doi.org/10.1155/2023/3371599
Saranga BGupta LSachdeva ASharma T(2023)Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT)10.1109/CSNT57126.2023.10134659(15-20)Online publication date: 8-Apr-2023
https://doi.org/10.1109/CSNT57126.2023.10134659
Leavline ESugantha A(2022)Reliability improved dual driven feedback 10T SRAM bit cellMicroelectronics Reliability10.1016/j.microrel.2022.114804139(114804)Online publication date: Dec-2022
https://doi.org/10.1016/j.microrel.2022.114804
Tahoori MGolanbari M(2020)Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data PathsJournal of Low Power Electronics and Applications10.3390/jlpea1004004210:4(42)Online publication date: 3-Dec-2020
https://doi.org/10.3390/jlpea10040042
Elmezayen MHu WMaghraby AAbougindia IAy S(2020)Accurate Analysis and Design of Integrated Single Input Schmitt Trigger CircuitsJournal of Low Power Electronics and Applications10.3390/jlpea1003002110:3(21)Online publication date: 29-Jun-2020
https://doi.org/10.3390/jlpea10030021
Lin ZChen PYe LYan XDong LZhang SYang ZPeng CWu XChen J(2020)Challenges and Solutions of the TFET Circuit DesignIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.3010803(1-14)Online publication date: 2020
https://doi.org/10.1109/TCSI.2020.3010803
Choudhury ASikdar B(2020)Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space ExplorationJournal of Electronic Testing10.1007/s10836-019-05852-6Online publication date: 18-Feb-2020
https://doi.org/10.1007/s10836-019-05852-6
Tseng HHuang PWu SLung SWang WHwang WChuang C(2019)28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications2019 32nd IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC46988.2019.1570555748(248-253)Online publication date: Sep-2019
https://doi.org/10.1109/SOCC46988.2019.1570555748
Yan CJoseph RJacob B(2018)CocoaProceedings of the International Symposium on Memory Systems10.1145/3240302.3240304(117-128)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240304
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