Article

Reducing cache energy consumption by tag encoding in embedded processors

Authors:

Mingming Zhang,

Ge ZhangAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 367 - 370

https://doi.org/10.1145/1283780.1283860

Published: 27 August 2007 Publication History

Abstract

This paper presents a new technique eliminating redundant cache tag and data accesses to reduce energy consumption. We assign a register to each tag in a cache to represent its state. Before starting an access, we can check the tag states in the target cache set to determine which way(s) should be accessed and which should not. Through this method, almost all the accesses in the I-cache can be directed to the target cache way immediately for most benchmark programs. For a 2-way set-associative cache, the energy consumption can be reduced by 76.6% compared with conventional cache architecture, and by 39.8% compared with Block Buffering, a simple but well-known technique. Besides, this approach does not require any special circuitry internal to the cache RAM such as row or column activation mechanisms. This is considered an important advantage in industry because of its easy implementation.

References

[1]

Montanaro, J.; Witek, R. T.; Anne, K. et al; "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor", Solid-State Circuits, IEEE Journal of, Volume 31, Issue 11, Nov. 1996 Page(s):1703--1714

[2]

Gowan, M. K.; Biro, L. L.; Jackson, D. B.; "Power considerations in the design of the Alpha 21264 microprocessor", Design Automation Conference, 1998. Proceedings, 15-19 Jun 1998 Page(s):726--731

Digital Library

[3]

Ching-Long Su; Despain, A. M.; "Cache designs for energy efficiency", System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on, Volume 1, 3-6 Jan. 1995 Page(s):306--315 vol.1

Digital Library

[4]

Kin, J.; Munish Gupta; Mangione-Smith, W. H.; "The filter cache: an energy efficient memory structure", Microarchitecture, 1997. Proceedings. Thirtieth Annual IEEE/ACM International Symposium on, 1-3 Dec. 1997 Page(s):184--193

Digital Library

[5]

Lea Hwang Lee; Moyer, B.; Arends, J.; "Instruction fetch energy reduction using loop caches for embedded applications with small tight loops", Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on, 1999 Page(s):267--269

Digital Library

[6]

Chia-Lin Yang; Chien-Hao Lee; "HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy Reduction", Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on, 9-11 Aug. 2004 Page(s):114--119

Digital Library

[7]

Inoue, K.; Ishihara, T.; Murakami, K.; "Way-predicting set-associative cache for high performance and low energy consumption", Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on, 1999 Page(s):273--275

Digital Library

[8]

C. Zhang, F. Vahid, J. Yang, et al. "A Way-Halting Cache for Low-Energy High-Performance Systems" IEEE Computer Architecture Letters, Vol. 2, 2003

Digital Library

[9]

Youtao Zhang; Jun Yang; "Low Cost Instruction Cache Designs for Tag Comparison Elimination", Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on, 25-27 Aug. 2003 Page(s):266--269

Digital Library

[10]

Nicolaescu, D.; Veidenbaum, A.; Nicolau, A.; "Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors", Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003 Page(s):1064--1068

Digital Library

[11]

Petrov, P.; Orailoglu, A.; "Tag compression for low power in dynamically customizable embedded processors", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume 23, Issue 7, July 2004 Page(s):1031--1047

Digital Library

[12]

Chuanjun Zhang; Vahid, F.; Najjar, W.; "Energy Benefits of a Configurable Line Size Cache for Embedded Systems", VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on, 20-21 Feb. 2003 Page(s):87--91

Digital Library

[13]

Chuanjun Zhang; Vahid, F.; Lysecky, R.; "A self-tuning cache architecture for embedded systems", Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, Volume 1, 16-20 Feb. 2004 Page(s):142--147 Vol.1

Digital Library

[14]

Yen-Jen Chang; Shanq-Jang Ruan; Feipei Lai; "Design and Analysis of Low-Power Cache Using Two-Level Filter Scheme", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume 11, Issue 4, Aug. 2003 Page(s):568--580

Digital Library

[15]

Lee, H.-H. S.; Ballapuram, C. S.; "Energy Efficient D-TLB and Data Cache Using Semantic-Aware Multilateral Partitioning", Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on, 25-27 Aug. 2003 Page(s):306--311

Digital Library

[16]

M. R. Guthaus, J. S. Ringenberg, D. Ernst, et al. "MiBench: A free, commercially representative embedded benchmark suite", Proceedings of IEEE International Workshop on Workload Characterization, Dec. 2001, pp 3--14

Digital Library

[17]

D. Burger and T. M. Austin, "The SimpleScalar tool set, version 2.0," TR-CS-1342, University of Wisconsin-Madison, June 1997.

Cited By

Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Wang LWang D(2016)Way prediction set-associative data cache for low power digital signal processors2016 IEEE 13th International Conference on Signal Processing (ICSP)10.1109/ICSP.2016.7877886(508-512)Online publication date: Nov-2016
https://doi.org/10.1109/ICSP.2016.7877886
Bunse CHöpfner HKlingert SMansour ERoychoudhury S(2014)Energy Aware Database ManagementEnergy-Efficient Data Centers10.1007/978-3-642-55149-9_4(40-53)Online publication date: 2014
https://doi.org/10.1007/978-3-642-55149-9_4
Show More Cited By

Index Terms

Reducing cache energy consumption by tag encoding in embedded processors
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Recommendations

A predictive decode filter cache for reducing power consumption in embedded processors

With advances in semiconductor technology, power management has increasingly become a very important design constraint in processor design. In embedded processors, instruction fetch and decode consume more than 40% of processor power. This calls for ...
An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors

Energy efficiency of cache memories is crucial in designing embedded processors. Reducing energy consumption in the instruction cache is especially important, since the instruction cache consumes a significant portion of total processor energy. This ...
An energy-efficient L2 cache architecture using way tag information under write-through policy

Many high-performance microprocessors employ cache write-through policy for performance improvement and at the same time achieving good tolerance to soft errors in on-chip caches. However, write-through policy also incurs large energy overhead due to ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 August 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISLPED07

Sponsor:

ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
253
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wu WZhu QWang FLin RQi F(2020)Compiler Optimizing for Power Efficiency of On-Chip MemoryAdvanced Computer Architecture10.1007/978-981-15-8135-9_21(290-303)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_21
Wang LWang D(2016)Way prediction set-associative data cache for low power digital signal processors2016 IEEE 13th International Conference on Signal Processing (ICSP)10.1109/ICSP.2016.7877886(508-512)Online publication date: Nov-2016
https://doi.org/10.1109/ICSP.2016.7877886
Bunse CHöpfner HKlingert SMansour ERoychoudhury S(2014)Energy Aware Database ManagementEnergy-Efficient Data Centers10.1007/978-3-642-55149-9_4(40-53)Online publication date: 2014
https://doi.org/10.1007/978-3-642-55149-9_4
Quanquan Li Qi Wang Tiejun Zhang Donghui Wang Chaohuan Hou (2013)Low power instruction cache design based on branch execution tracks2013 IEEE 10th International Conference on ASIC10.1109/ASICON.2013.6811822(1-4)Online publication date: Oct-2013
https://doi.org/10.1109/ASICON.2013.6811822
Cho HChoi JJhang SJhon C(2012)Low Power Instruction Cache with Word Selective Line BufferProceedings of the 2012 IEEE 15th International Conference on Computational Science and Engineering10.1109/ICCSE.2012.37(215-222)Online publication date: 5-Dec-2012
https://dl.acm.org/doi/10.1109/ICCSE.2012.37
Berticelli Lo TBeck ARutzig MCarro L(2010)A low-energy approach for context memory in reconfigurable systems2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)10.1109/IPDPSW.2010.5470745(1-8)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPSW.2010.5470745
Bunse CHopfner HMansour ERoychoudhury S(2009)Exploring the Energy Consumption of Data Sorting Algorithms in Embedded and Mobile EnvironmentsProceedings of the 2009 Tenth International Conference on Mobile Data Management: Systems, Services and Middleware10.1109/MDM.2009.103(600-607)Online publication date: 18-May-2009
https://dl.acm.org/doi/10.1109/MDM.2009.103
Kalyan TMutyam MNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Word-interleaved cacheProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393991(265-270)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393991

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents