Article

Fragment cache management for dynamic binary translators in embedded systems with scratchpad

Authors:

Bruce R. Childers,

Jack W. Davidson,

Jason D. Hiser,

Jonathan MisurdaAuthors Info & Claims

CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 75 - 84

https://doi.org/10.1145/1289881.1289898

Published: 30 September 2007 Publication History

Abstract

Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for embedded systems. However, a challenge to DBT in this domain is stringent constraints on memory and performance. The translated code buffer used by DBT may occupy too much memory space. This paper proposes novel schemes to manage this buffer with scratchpad memory. We use footprint reduction to minimize the space needed by the translated code, victim compression to reduce the cost of retranslating previously seen code, and fragment pinning to avoid evicting needed code. We comprehensively evaluate our techniques to demonstrate their effectiveness.

References

[1]

T. Austin, E. Larson and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling", IEEE Computer, Vol. 35, No. 2, February 2002.

Digital Library

[2]

V. Bala, E. Duesterwald, and S. Banerjia, "Dynamo: A transparent dynamic optimization system", Programming Language Design and Implementation, 2000.

Digital Library

[3]

D. Bruening, T. Garnett and S. Amarasinghe, "An infrastructure for adaptive dynamic optimization", Int'l. Symp. on Code Generation and Optimization, 2003.

Digital Library

[4]

D. Bruening and S. Amarasinghe, "Maintaining Consistency and Boundary Capacity of Software Code Caches", Int'l. Symp. on Code Generation and Optimization, 2005.

Digital Library

[5]

D. Bruening, V. Kiriansky, T. Garneet and S. Banerji, "Thread-Shared Software Code Caches", Int'l. Symp. on Code Generation and Optimization, 2006.

Digital Library

[6]

G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, and J. A. Fisher, "DELI: A new run-time control point", Int'l.Symp. on Microarchitecture, 2002.

Digital Library

[7]

B. Egger, C. Kin, C. Jang, Y. Nam, J. Lee and S. L. Min, "A Dynamic Code Placement Technique for Scratchpad Memory Using Postpass Optimization", Conf. Compilers, Architecture, and Synthesis for Embedded Systems, 2006.

Digital Library

[8]

B. Egger, J. Lee and H. Shin, "Scratchpad Memory Management for Portable Systems with a Memory Management Unit", Conf. Embedded Software, 2006.

Digital Library

[9]

A. Guha, K. Hazelwood and M. L. Soffa, "Reducing Exit Stub Memory Consumption in Code Caches", High Performance Embedded Architectures and Compilers, 2007.

Digital Library

[10]

M. R Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, "MiBench: A Free Commercially Representative Embedded Benchmark Suite", IEEE 4th Workshop on Workload Characterization, 2001.

Digital Library

[11]

K. Hazelwood and M. D. Smith, "Managing Bounded Code Caches in Dynamic Binary Optimization Systems", ACM Trans. on Architecture and Code Optimization, Vol. 3, No. 3, September 2006.

Digital Library

[12]

J. D. Hiser, D. Williams, W. Hu, J. W. Davidson, J. Mars and B. R. Childers, "Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems", Int'l. Symp. on Code Generation and Optimization, 2007.

Digital Library

[13]

J. D. Hiser, D. Williams, A. Filipi, J. W. Davidson and B. R. Childers, "Evaluating Fragment Creation Policies for SDT Systems", Virtual Execution Environments Conf., 2006.

Digital Library

[14]

Intel, Intel PXA27x Processor Family, document number 280004-002, August 2004.

[15]

N. P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers", Int'l. Symp. on Computer Architecture, 1990.

Digital Library

[16]

T. Kemp, R. Montoye, J. Harper, J. Palmer, and D. Auerbach, "A decompression core for PowerPC", IBM Journal of Research and Development, 42(6), Nov. 1998.

Digital Library

[17]

V. Kiriansky, D. Bruening and S. Amarasinghe, "Secure execution via program shepherding", USENIX Security, 2002.

Digital Library

[18]

C. Luk, R. Cohn, R. Muth, et. al, "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation", Conf. on Programming Design and Implementation, 2005.

Digital Library

[19]

J. E. Miller and A. Agarwal, "Software-based Instruction Caching for Embedded Processors", Conf. on Architectural Support for Programming Languages and Operating Systems, 2006.

Digital Library

[20]

N. Nguyen, A. Dominguez and R. Barua, "Memory Allocation for Embedded Systems with a Compile-Time-Unknown Scratch-Pad Size", Conf. Compilers, Architecture, and Synthesis for Embedded Systems, 2005.

Digital Library

[21]

K. Scott, N. Kumar, S. Veluswamy, B. Childers, J. Davidson, M. L. Soffa, "Reconfigurable and retargetable software dynamic translation", Symp. on Code Generation and Optimization, 2003.

Digital Library

[22]

K. Scott and J. Davidson, "Safe virtual execution using software dynamic translation", Annual Computer Security Applications Conference, 2002.

Digital Library

[23]

S. Shogan and B. R. Childers. "Compact Binaries with Code Compression in a Software Dynamic Translator," Conf. Design Automation and Test in Europe, 2004.

Digital Library

[24]

S. Sridhar, J. S. Shapiro, E. Northup, P. P. Bungale, "HDTrans: An open source, low-level dynamic instrumentation system", Virtual Execution Environments Conf., 2006.

Digital Library

[25]

S. Steinke, L. Wehmeyer, B. Lee and P. Marwedel, "Assigning Program and Data Objects to Scratchpad for Energy Reduction", Conf. Design, Automation and Test in Europe, 2002.

Digital Library

[26]

Q. Wu, M. Martonosi, D. W. Clark, Y. Reddi, D. Connors, Y. Wu, J. Lee, and D. Brooks, "A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance", Int'l. Symp. on Microarchitecture, 2005.

Digital Library

[27]

S. Zhou, B. R. Childers, and M. L. Soffa. Planning for Code Buffer Management in Distributed Virtual Execution Environments, Virtual Execution Environments Conf., 2005.

Digital Library

Cited By

Yarza IAzkarate-askasua MGrüttner KNebel WChillet D(2018)Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMUProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180671(1-8)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180671
Chen JYang WHsu WShen BOu Q(2017)On Static Binary Translation of ARM/Thumb Mixed ISA BinariesACM Transactions on Embedded Computing Systems10.1145/299645816:3(1-25)Online publication date: 28-Mar-2017
https://dl.acm.org/doi/10.1145/2996458
Hsu CHong DHsu WLiu PWu J(2015)A dynamic binary translation system in a client/server environmentJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.05.00261:7(307-319)Online publication date: 1-Aug-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.05.002
Show More Cited By

Index Terms

Fragment cache management for dynamic binary translators in embedded systems with scratchpad
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

Recommendations

Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
DAC '09: Proceedings of the 46th Annual Design Automation Conference

Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-purpose systems, embedded systems often have specialized memory resources, ...
Dynamic scratchpad memory management for code in portable systems with an MMU

In this work, we present a dynamic memory allocation technique for a novel, horizontally partitioned memory subsystem targeting contemporary embedded processors with a memory management unit (MMU). We propose to replace the on-chip instruction cache ...
Enabling dynamic binary translation in embedded systems with scratchpad memory

Important challenges for embedded systems can be addressed by dynamic binary translation. A dynamic binary translator stores translated instructions in a software-managed code cache, which is usually large to minimize overhead. This article shows how to ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

September 2007

292 pages

ISBN:9781595938268

DOI:10.1145/1289881

General Chairs:
Taewhan Kim
Seoul National University, South Korea
,
Pascal Sainrat
IRIT - Université de Toulouse, France
,
Program Chairs:
Steven S. Lumetta
University of Illinois at Urbana-Champaign, USA
,
Nacho Navarro
Universitat Politecnica de Catalunya, Spain

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

Acceptance Rates

Overall Acceptance Rate 52 of 230 submissions, 23%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

21
Total Citations
View Citations
338
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Yarza IAzkarate-askasua MGrüttner KNebel WChillet D(2018)Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMUProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180671(1-8)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180671
Chen JYang WHsu WShen BOu Q(2017)On Static Binary Translation of ARM/Thumb Mixed ISA BinariesACM Transactions on Embedded Computing Systems10.1145/299645816:3(1-25)Online publication date: 28-Mar-2017
https://dl.acm.org/doi/10.1145/2996458
Hsu CHong DHsu WLiu PWu J(2015)A dynamic binary translation system in a client/server environmentJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.05.00261:7(307-319)Online publication date: 1-Aug-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.05.002
Shen BHsu WYang W(2014)A Retargetable Static Binary Translator for the ARM ArchitectureACM Transactions on Architecture and Code Optimization10.1145/262933511:2(1-25)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2629335
Chen JShen BOu QYang WHsu WRabbah RRaghunathan A(2013)Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translatorProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555748(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555748
Baiocchi JChilders BDavidson JHiser J(2013)Enabling dynamic binary translation in embedded systems with scratchpad memoryACM Transactions on Embedded Computing Systems10.1145/2362336.239917811:4(1-33)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1145/2362336.2399178
Chen HYang C(2013)Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptation2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662528(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662528
Chen JShen BOu QYang WHsu W(2013)Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translator2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662525(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662525
Charles HLhuillier YCarbon A(2013)Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systemsProceedings of the 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2013.6567576(203-210)Online publication date: 5-Jun-2013
https://dl.acm.org/doi/10.1109/ASAP.2013.6567576
Guha AHazelwood KSoffa M(2012)Memory optimization of dynamic binary translators for embedded systemsACM Transactions on Architecture and Code Optimization10.1145/2355585.23555959:3(1-29)Online publication date: 5-Oct-2012
https://dl.acm.org/doi/10.1145/2355585.2355595
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten