research-article

RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm

Authors:

Michael D. Moffitt,

Charles J. Alpert, and

Igor L. MarkovAuthors Info & Claims

ISPD '08: Proceedings of the 2008 international symposium on Physical design

April 2008

Pages 2 - 9

https://doi.org/10.1145/1353629.1353633

Published: 13 April 2008 Publication History

Abstract

Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called RUMBLE (Rip Up and Move Boxes with Linear Evaluation) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design

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Cited By

Fu CTrombley BXiang HNam GHu J(2023)Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238658(1-6)Online publication date: 20-Jun-2023
https://doi.org/10.1109/ISVLSI59464.2023.10238658
Chentouf MEl Abidine Alaoui Ismaili Z(2022)A PUS based nets weighting mechanism for power, hold, and setup timing optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2022.01.00684:C(122-130)Online publication date: 1-May-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.01.006
Jung JNam GReddy LJiang IShin Y(2018)OWARUIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277427737:9(1825-1838)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2774277
Show More Cited By

Index Terms

RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm

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Published In

cover image ACM Conferences

ISPD '08: Proceedings of the 2008 international symposium on Physical design

April 2008

218 pages

ISBN:9781605580487

DOI:10.1145/1353629

General Chair:
David Z. Pan
University of Texas at Austin
,
Program Chair:
Gi-Joon Nam
IBM Research

Copyright © 2008 ACM.

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Publication History

Published: 13 April 2008

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ISPD '08

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ISPD '08: International Symposium on Physical Design

April 13 - 16, 2008

Oregon, Portland, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Citations

Cited By

Fu CTrombley BXiang HNam GHu J(2023)Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238658(1-6)Online publication date: 20-Jun-2023
https://doi.org/10.1109/ISVLSI59464.2023.10238658
Chentouf MEl Abidine Alaoui Ismaili Z(2022)A PUS based nets weighting mechanism for power, hold, and setup timing optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2022.01.00684:C(122-130)Online publication date: 1-May-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.01.006
Jung JNam GReddy LJiang IShin Y(2018)OWARUIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277427737:9(1825-1838)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2774277
Flach GFogaça MMonteiro JJohann MReis RYoung EOzdal M(2016)Drive Strength Aware Cell Movement Techniques for Timing Driven PlacementProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872359(73-80)Online publication date: 3-Apr-2016
https://dl.acm.org/doi/10.1145/2872334.2872359
Livramento VNetto RGuth CGüntzel JSantos L(2016)Clock-Tree-Aware Incremental Timing-Driven PlacementACM Transactions on Design Automation of Electronic Systems10.1145/285879321:3(1-27)Online publication date: 19-Apr-2016
https://dl.acm.org/doi/10.1145/2858793
Netto RLivramento VGuth Cdos Santos LGuntzel J(2016)Evaluating the impact of circuit legalization on incremental optimization techniques2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2016.7724041(1-6)Online publication date: Aug-2016
https://doi.org/10.1109/SBCCI.2016.7724041
Monteiro JDarav NFlach GFogaca MReis RKennings AJohann MBehjat L(2016)Routing-Aware Incremental Timing-Driven Placement2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2016.23(290-295)Online publication date: Jul-2016
https://doi.org/10.1109/ISVLSI.2016.23
Bock AHeld SKämmerling NSchorr U(2015)Local search algorithms for timing-driven placement under arbitrary delay modelsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744867(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744867
Kim MHu JLi JViswanathan N(2015)ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372671(921-926)Online publication date: Nov-2015
https://doi.org/10.1109/ICCAD.2015.7372671
Kim MHuj JViswanathan N(2014)ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite: Special session paper: CAD contest2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001376(361-366)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001376
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