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Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga

Authors:

Ernesto Ordoñez-Cardenas,

Rene de J. Romero-TroncosoAuthors Info & Claims

GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI

Pages 333 - 338

https://doi.org/10.1145/1366110.1366188

Published: 04 May 2008 Publication History

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Abstract

This paper presents an implementation of a multilayer perceptronneural network and the backpropagation learning algorithm in an FPGA. The resulting implementation, in contrast to others, is a low-cost system with effective resource utilization, capable of training the neural network for any given task. The system is based on a modular scheme conforming to a system-on-a-chip (SoC), where modules can be replaced or scaled to suit a specific application. The system uses fixed-point arithmetic and it was carried out using generic hardware description language. A pipeline architecture is used in order to build a time-efficient system. The efficacy of the systems was tested in a pattern recognition application, tests were done in a low-cost Xilinx Spartan-3E FPGA.

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https://doi.org/10.1109/SENSORS56945.2023.10324900
Zhou XDu ZZhang SZhang LLan HLiu SLi LGuo QChen TChen Y(2019)Addressing Sparsity in Deep Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286428938:10(1858-1871)Online publication date: Oct-2019
https://doi.org/10.1109/TCAD.2018.2864289
Bai YFan DLin M(2018)Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural NetworksIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27871094:3(463-476)Online publication date: 1-Jul-2018
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Index Terms

Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI

May 2008

480 pages

ISBN:9781595939999

DOI:10.1145/1366110

General Chairs:
Vijay Narayanan
Penn State University
,
Zhiyuan Yan
Lehigh University
,
Program Chairs:
Enrico Macii
Politecnico di Torino
,
Sanjukta Bhanja
University of South Florida

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 May 2008

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May 4 - 6, 2008

Florida, Orlando, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Wu HNguyen DChao P(2023)Implementing a Personalized Model in Edge via FPGA for Non-Invasive Blood Flow Volume Measurement Based on PPG for Security2023 IEEE SENSORS10.1109/SENSORS56945.2023.10324900(1-4)Online publication date: 29-Oct-2023
https://doi.org/10.1109/SENSORS56945.2023.10324900
Zhou XDu ZZhang SZhang LLan HLiu SLi LGuo QChen TChen Y(2019)Addressing Sparsity in Deep Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286428938:10(1858-1871)Online publication date: Oct-2019
https://doi.org/10.1109/TCAD.2018.2864289
Bai YFan DLin M(2018)Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural NetworksIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27871094:3(463-476)Online publication date: 1-Jul-2018
https://doi.org/10.1109/TMSCS.2017.2787109
Li ZWang YZhi TChen T(2017)A survey of neural network acceleratorsFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-016-6159-111:5(746-761)Online publication date: 1-Oct-2017
https://dl.acm.org/doi/10.1007/s11704-016-6159-1
Zhang SDu ZZhang LLan HLiu SLi LGuo QChen TChen YHsu WYang CLipasti MLee H(2016)Cambricon-xThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195662(1-12)Online publication date: 15-Oct-2016
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Jung YStratos KCarloni LGangemi ALeonardi SPanconesi A(2015)LN-AnnoteProceedings of the 24th International Conference on World Wide Web10.1145/2736277.2741633(538-548)Online publication date: 18-May-2015
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Ahmad IAbdulah AAlghamdi A(2010)Towards the designing of a robust intrusion detection system through an optimized advancement of neural networksProceedings of the 2010 international conference on Advances in computer science and information technology10.5555/1875558.1875615(597-602)Online publication date: 23-Jun-2010
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Ahmad IAbdulah AAlghamdi A(2010)Towards the Designing of a Robust Intrusion Detection System through an Optimized Advancement of Neural NetworksAdvances in Computer Science and Information Technology10.1007/978-3-642-13577-4_53(597-602)Online publication date: 2010
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FPGA Implementation of a Pipelined On-Line Backpropagation

Artificial neural network implementation on a single FPGA of a pipelined on-line backpropagation

A parameterizable handel-C neural network implementation for FPGA

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