research-article

Copy coalescing by graph recoloring

Authors:

Sebastian Hack,

Gerhard GoosAuthors Info & Claims

ACM SIGPLAN Notices, Volume 43, Issue 6

Pages 227 - 237

https://doi.org/10.1145/1379022.1375610

Published: 07 June 2008 Publication History

Abstract

Register allocation is always a trade-off between live-range splitting and coalescing. Live-range splitting generally leads to less spilling at the cost of inserting shuffle code. Coalescing removes shuffle code while potentially raising the register demand and causing spilling.

Recent research showed that the live-range splitting of the SSA form's Æ-functions leads to chordal interference graphs. This improves upon two long-standing inconveniences of graph coloring register allocation: First, chordal graphs are optimally colorable in quadratic time. Second, the number of colors needed to color the graph is equal to the maximal register pressure in the program. However, the inserted shuffle code incurred by the Æ-functions can slow down the program severely. Hence, to make such an approach work in practice, a coalescing technique is needed that removes most of the shuffle code without causing further spilling.

In this paper, we present a coalescing technique designed for, but not limited to, SSA-form register allocation. We exploit that a valid coloring can be easily obtained by an SSA-based register allocator. This initial coloring is then improved by recoloring the interference graph and assigning shuffle-code related nodes the same color. Thereby, we always keep the coloring of the graph valid. Hence, the coalescing is safe, i. e. no spill code will be caused by coalescing.

Comparing to iterated register coalescing, the state of the art in safe coalescing, our method is able to remove 22.5% of the costs and 44.3% of the copies iterated coalescing left over. The best solution possible, found by a colaescer using integer linear programming (ILP), was 35.9% of the costs and 51.9% of the copies iterated coalescing left over. The runtime of programs compiled with our heuristic matches that of the programs compiled with the ILP technique.

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Cited By

Buchwald SMohr MRutter I(2015)Optimal Shuffle Code with Permutation InstructionsAlgorithms and Data Structures10.1007/978-3-319-21840-3_44(528-541)Online publication date: 28-Jul-2015
https://doi.org/10.1007/978-3-319-21840-3_44
Mohr MGrudnitsky AModschiedler TBauer LHack SHenkel JRabbah RRaghunathan A(2013)Hardware acceleration for programs in SSA formProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555743(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555743
Mohr MGrudnitsky AModschiedler TBauer LHack SHenkel J(2013)Hardware acceleration for programs in SSA form2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662518(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662518
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Index Terms

Copy coalescing by graph recoloring
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

Recommendations

Copy coalescing by graph recoloring
PLDI '08: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation

Register allocation is always a trade-off between live-range splitting and coalescing. Live-range splitting generally leads to less spilling at the cost of inserting shuffle code. Coalescing removes shuffle code while potentially raising the register ...
Optimistic register coalescing

Graph-coloring register allocators eliminate copies by coalescing the source and target nodes of a copy if they do not interfere in the interference graph. Coalescing, however, can be harmful to the colorability of the graph because it tends to yield a ...
Iterated register coalescing

An important function of any register allocator is to target registers so as to eliminate copy instructions. Graph-coloring register allocation is an elegant approach to this problem. If the source and destination of a move instruction do not interfere, ...

Reviews

Reviewer: Charles Robert Morgan

This paper is a continuation of a recent revolution in graph coloring register allocation based on the work of Chaitin and others. Chaitin's technique has two drawbacks: repeated building of an expensive data structure called the interference graph and determining which data to keep in registers when insufficient registers are available. Hack and a number of other authors determined that programs represented in static single assignment form can be colored without building the interference graph, since the interference graph is a chordal graph. Unfortunately, there is a drawback: the coloring may produce a number of register-to-register move instructions. This often occurs when two operands of an instruction must be in the same register or an operand must be in a fixed physical register. Removing these move instructions is called copy coalescing. This paper provides a more advanced algorithm for copy coalescing than was provided in Hack's thesis. It uses the move instructions to partition the set of symbolic registers. Ideally, all elements of each partition should be in the same physical register; of course, this is not always possible. It applies a recursive algorithm to adjust the color of each symbolic register. The algorithm has a number of limits built in, to avoid excessive computation. This is a promising algorithm. It was tested against the integer subset of the CPU2000 SPEC benchmark. Other programs, particularly floating-point intensive programs and machine-generated programs, have much larger basic blocks and heavier register usage. We need to see results indicating that the algorithms can realistically handle tens of thousands of symbolic registers and huge functions. Online Computing Reviews Service

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 43, Issue 6

PLDI '08

June 2008

382 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1379022

Issue’s Table of Contents

PLDI '08: Proceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation
June 2008
396 pages
ISBN:9781595938602
DOI:10.1145/1375581
General Chair:
Rajiv Gupta
University of California, Riverside, USA
,
Program Chair:
Saman Amarasinghe
Massachusetts Institute of Technology, USA

Copyright © 2008 ACM.

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Association for Computing Machinery

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Publication History

Published: 07 June 2008

Published in SIGPLAN Volume 43, Issue 6

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Citations

Cited By

Buchwald SMohr MRutter I(2015)Optimal Shuffle Code with Permutation InstructionsAlgorithms and Data Structures10.1007/978-3-319-21840-3_44(528-541)Online publication date: 28-Jul-2015
https://doi.org/10.1007/978-3-319-21840-3_44
Mohr MGrudnitsky AModschiedler TBauer LHack SHenkel JRabbah RRaghunathan A(2013)Hardware acceleration for programs in SSA formProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555743(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555743
Mohr MGrudnitsky AModschiedler TBauer LHack SHenkel J(2013)Hardware acceleration for programs in SSA form2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662518(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662518
Philippidis CShang W(2010)On minimizing register usage of linearly scheduled algorithms with uniform dependenciesComputer Languages, Systems and Structures10.1016/j.cl.2009.12.00136:3(250-267)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1016/j.cl.2009.12.001
Levin M(2009)Combinatorial optimization in system configuration designAutomation and Remote Control10.1134/S000511790903018770:3(519-561)Online publication date: 1-Mar-2009
https://dl.acm.org/doi/10.1134/S0005117909030187
Chandrasekhar AChen GChen PChen WGu JGuo PKumar SLueh GMistry PPan WRaoux TTrifunovic KKandemir MJimborean AMoseley T(2019)IGC: the open source Intel graphics compilerProceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization10.5555/3314872.3314902(254-265)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.5555/3314872.3314902
Chandrasekhar AChen GChen PChen WGu JGuo PKumar SLueh GMistry PPan WRaoux TTrifunovic K(2019)IGC: The Open Source Intel Graphics Compiler2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO.2019.8661189(254-265)Online publication date: Feb-2019
https://doi.org/10.1109/CGO.2019.8661189
Hayes ALi LChavarría-Miranda DSong SZhang E(2016)OrionProceedings of the 17th International Middleware Conference10.1145/2988336.2988355(1-13)Online publication date: 28-Nov-2016
https://dl.acm.org/doi/10.1145/2988336.2988355
Barik RZhao JSarkar V(2013)A decoupled non-SSA global register allocation using bipartite liveness graphsACM Transactions on Architecture and Code Optimization10.1145/254410110:4(1-24)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2544101
Brandner FColombet Q(2013)Elimination of parallel copies using code motion on data dependence graphsComputer Languages, Systems and Structures10.1016/j.cl.2012.09.00139:1(25-47)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1016/j.cl.2012.09.001
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