research-article

A practical approach of memory access parallelization to exploit multiple off-chip DDR memories

Authors:

Woo-Cheol Kwon,

Kyu-Myung Choi,

Soo-Kwan EoAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 447 - 452

https://doi.org/10.1145/1391469.1391585

Published: 08 June 2008 Publication History

Abstract

3D stacked memory enables more off-chip DDR memories. Redesigning existing IPs to exploit the increased memory parallelism will be prohibitively costly. In our work, we propose a practical approach to exploit the increased bandwidth and reduced latency of multiple off-chip DDR memories while reusing existing IPs without modification. The proposed approach is based on two new concepts: transaction id renaming and distributed soft arbitration. We present two on-chip network components, request parallelizer and read data serializer, to realize the concepts. Experiments with synthetic test cases and an industrial strength DTV SoC design show that the proposed approach gives significant improvements in total execution cycle (21.6%) and average memory access latency (31.6%) in the DTV case with a small area overhead (30.1% in the on-chip network, and less than 1.4% in the entire chip).

References

[1]

F. Li, et. al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory", Proc. ISCA, 2006.

Digital Library

[2]

L. Hsu, et. al., "Exploring the Cache Design Space for Large Scale CMPs", SIGARCH Computer Architecture News, pp. 24--33, 33(4), 2005.

Digital Library

[3]

S. Borkar, "Thousand-Core Chips - A Technology Perspective", Proc. DAC, 2007.

Digital Library

[4]

B. So, M. W. Hall and H. E. Ziegler, "Custom Data Layout for Memory Parallelism", Proc. International Symposium on Code Generation and Optimization, 2004.

Digital Library

[5]

B. Mathew, S. McKee, J. Carter, and A. Davis, "Design of a parallel vector access unit for SDRAM memory systems", Proc. HPCA, 1999.

[6]

K. Kim and V. K. Prasanna, "Latin square for parallel array access", IEEE Trans. on Parallel and Distributed Systems, 4(4), April 1993.

Digital Library

[7]

M. Franklin and G. S. Sohi, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References", IEEE Trans. on Computers, 45(5), May 1996.

Digital Library

[8]

Sonics MemMAX 2.0 Datasheet, available at www.sonicsinc.com.

[9]

AMBA3 protocol and Fabric IPs, available at http://www.arm.com/products/index.html.

[10]

T. Ezaki, et. al., "A 160Gb/s Interface Design Configuration for Multichip LSI", Proc. ISSCC, 2004.

[11]

D. Mosberger, "Memory Consistency Models", Operating Systems Review, 17(1), Jan. 1993.

Digital Library

[12]

DesignWare® IP Solutions for AMBA#8482; Infrastructure & Fabric, available at www.synopsys.com.

[13]

W. Kwon, et. al., "An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication", Proc. DATE, 2008.

Digital Library

[14]

Y. Lin, "Design Challenge of a QuadHDTV Video Decoder", MPSoC School, 2007, available at tima.imag.fr/mpsoc.

[15]

A. Harris, et. al., "Bus deadlock avoidance", United States Patent 7219178, 2007.

Cited By

Wang BLu Z(2020)Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core ArchitectureIEEE Access10.1109/ACCESS.2020.30290148(182663-182678)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3029014
Lin YYang CHuang JLin THsueh CChang N(2015)System-Level Performance and Power Optimization for MPSoCACM Transactions on Embedded Computing Systems10.1145/265633914:1(1-26)Online publication date: 21-Jan-2015
https://dl.acm.org/doi/10.1145/2656339
Du GLi MLu ZGao MWang C(2014)An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NOCS.2014.7008761(49-56)Online publication date: Sep-2014
https://doi.org/10.1109/NOCS.2014.7008761
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Index Terms

A practical approach of memory access parallelization to exploit multiple off-chip DDR memories
1. Hardware
  1. Integrated circuits

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2008

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Wang BLu Z(2020)Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core ArchitectureIEEE Access10.1109/ACCESS.2020.30290148(182663-182678)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3029014
Lin YYang CHuang JLin THsueh CChang N(2015)System-Level Performance and Power Optimization for MPSoCACM Transactions on Embedded Computing Systems10.1145/265633914:1(1-26)Online publication date: 21-Jan-2015
https://dl.acm.org/doi/10.1145/2656339
Du GLi MLu ZGao MWang C(2014)An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)10.1109/NOCS.2014.7008761(49-56)Online publication date: Sep-2014
https://doi.org/10.1109/NOCS.2014.7008761
Daneshtalab MEbrahimi MPlosila JTenhunen HMacii E(2013)CARSProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485539(1048-1051)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485539
Kim DYoo SLee S(2013)A network congestion-aware memory subsystem for manycoreACM Transactions on Embedded Computing Systems10.1145/2485984.248599812:4(1-18)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2485984.2485998
Daneshtalab MEbrahimi MLiljeberg PPlosila JTenhunen H(2013)A systematic reordering mechanism for on-chip networks using efficient congestion-aware methodJournal of Systems Architecture10.1016/j.sysarc.2012.01.00259:4-5(213-222)Online publication date: Apr-2013
https://doi.org/10.1016/j.sysarc.2012.01.002
Daneshtalab MEbrahimi MLiljeberg PPlosila JTenhunen H(2012)Memory-Efficient On-Chip Network With Adaptive InterfacesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216034831:1(146-159)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2160348
Daneshtalab MEbrahimi MLiljeberg PPlosila JTenhunen H(2012)Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International10.1109/3DIC.2012.6263024(1-8)Online publication date: Jan-2012
https://doi.org/10.1109/3DIC.2012.6263024
Jang WPan D(2011)Application-Aware NoC Design for Efficient SDRAM AccessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216017630:10(1521-1533)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2160176
Dongki Kim Sungjoo Yoo Sunggu Lee Jung Ho Ahn Hyunuk Jung (2011)A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763214(1-6)Online publication date: Mar-2011
https://doi.org/10.1109/DATE.2011.5763214
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