research-article

Leakage power reduction using stress-enhanced layouts

Authors:

Dennis Sylvester,

Kanak AgarwalAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 912 - 917

https://doi.org/10.1145/1391469.1391700

Published: 08 June 2008 Publication History

Abstract

In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as t_ox, V_th, and V_dd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based, performance-enhanced standard cell assignment with dual-V_th assignment. We study how stress-induced performance enhancements are affected by layout properties and improve standard cell layouts so that performance gains are maximized. We then develop a circuit-level, block-based, stress-enhanced optimization algorithm that includes all layout-dependent sources of mechanical stress. By combining the two performance enhancement techniques (stress-based and dual-V_th) for a set of benchmark circuits, we find that our stress-aware optimization, decreases leakage by ~24% on average, for iso-delay, when compared to dual-V_th assignment. Similarly, for iso-leakage, our optimization algorithm reduces delay on average by 5%. In both cases, the proposed method only incurs a small area penalty (< 0.5%).

References

[1]

F. Andrieu et al., "Experimental and Comparative Investigation of Low and High Field Transport in Substrate- and Process-Induced Strained Nanoscale MOSFETs," in Proc. VLSI Tech. Symp. Tech. Dig., pp. 176--177, 2005.

[2]

K. Mistry et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology," in Proc. VLSI Technol. Symp. Tech. Dig., pp. 50--51, 2005.

[3]

S. Wolf, "Silicon Processing for the VLSI Era," Lattice Press, 1995.

[4]

A. Chandrakasan et al., "Design of High-Performance Microprocessor Circuits," in IEEE press, 2001.

Digital Library

[5]

S. Sirichotiyakul et al., "Duet: An Accurate Leakage Estimation and Optimization Tool for Dual-V _t, Circuits," IEEE Trans. on VLSI Systems, Vol. 10, No. 2, pp. 79--90, April 2002.

Digital Library

[6]

L. Wei et al., "Design and optimization of low voltage high performance dual threshold CMOS circuits," in Proc. 35th Design Automation Conference, pp. 489--494, 1998.

Digital Library

[7]

D. Sylvester and A. Srivastava, "Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS,", in Proc. of the IEEE, Vol. 95, pp. 507--529, March 2007.

[8]

R. A. Bianchi et al., "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," in Proc. IEDM, pp. 117--120, 2002.

[9]

A. Kahng et al., "Exploiting STI Stress for Performance," in Proc. ICCAD, November 2007.

Digital Library

[10]

V. Moroz et al., "The Impact of Layout on Stress-Enhanced Transistor Performance," in Proc. SISPAD, pp. 143--146, 2005.

[11]

M. V. Dunga et al., "Modeling Advanced FET Technology in a Compact Model," in IEEE Trans. on Elect. Dev., Vol. 53, No. 9, pp. 1971--1978, September 2006.

[12]

V. Joshi et al., "Stress Aware Layout Optimization," in Proc. ISPD 2008, to appear April 2008.

Digital Library

[13]

V. Chan et al., "Strain for PMOS performance Improvement," in Proc. CICC, pp. 667--674, 2005.

[14]

W. H. Lee et al., "High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL," in Proc. IEDM, 2005.

[15]

H. S. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing," in Proc. IEDM, pp. 1075--1077, 2004.

[16]

K. Ota et al., "Novel locally strained channel technique for high performance 55nm CMOS," in Proc. IEDM, pp. 27--30, 2002.

[17]

Z. Luo et al., "Design of high performance PFETs with strained si channel and laser anneal," in Proc. IEDM, pp. 489--492, 2005.

[18]

Manual, Davinci 3D TCAD, Version 2005.10.

[19]

Manual, Synopsys TSUPREM4, Version 2007.03.

[20]

A. Dharchoudhury et al., "Transistor-level sizing and timing verification of domino circuits in the powerPC#8482; microprocessor," in Proc. ICCD, pp. 143--148, Oct. 1997.

Digital Library

[21]

V. Zyuban et al., "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels," in Proc. ISLPED, pp. 166--171, August 2002.

Digital Library

[22]

S. Burns et al., "Comparative Analysis of Conventional and Statistical Design Techniques," in Proc. 44th Design Automation Conference, pp 238--243, June 2007.

Digital Library

Cited By

Alam ILi TBrock SGupta P(2023)DRDebug: Automated Design Rule DebuggingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317472242:2(606-615)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3174722
Nayak SLodha SGanguly S(2021)Stress Engineering for Drive Current Enhancement in Silicon Carbide (SiC) Power MOSFETsIEEE Journal of the Electron Devices Society10.1109/JEDS.2021.31160989(876-880)Online publication date: 2021
https://doi.org/10.1109/JEDS.2021.3116098
Aghababa HKolahdouz MForouzandeh B(2016)Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833675(120-127)Online publication date: Sep-2016
https://doi.org/10.1109/PATMOS.2016.7833675
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Index Terms

Leakage power reduction using stress-enhanced layouts
1. Hardware
  1. Robustness

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 08 June 2008

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DAC '08

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Alam ILi TBrock SGupta P(2023)DRDebug: Automated Design Rule DebuggingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317472242:2(606-615)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3174722
Nayak SLodha SGanguly S(2021)Stress Engineering for Drive Current Enhancement in Silicon Carbide (SiC) Power MOSFETsIEEE Journal of the Electron Devices Society10.1109/JEDS.2021.31160989(876-880)Online publication date: 2021
https://doi.org/10.1109/JEDS.2021.3116098
Aghababa HKolahdouz MForouzandeh B(2016)Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2016.7833675(120-127)Online publication date: Sep-2016
https://doi.org/10.1109/PATMOS.2016.7833675
CHEN GZHANG YDONG QLI MNAKATAKE S(2015)Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADCIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E98.A.1442E98.A:7(1442-1454)Online publication date: 2015
https://doi.org/10.1587/transfun.E98.A.1442
Choy JSukharev VKteyan AHovsepyan HVenkatraman RCastagnetti R(2015)Post placement leakage reduction with stress-enhanced filler cells2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2015.7273531(303-308)Online publication date: Jul-2015
https://doi.org/10.1109/ISLPED.2015.7273531
Kahng ALee HCavallaro JZhang TJones ALi H(2014)Minimum implant area-aware gate sizing and placementProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591542(57-62)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591542
Su PLi Y(2014)Design optimization of 16-nm bulk FinFET technology via geometric programming2014 International Workshop on Computational Electronics (IWCE)10.1109/IWCE.2014.6865878(1-4)Online publication date: Jun-2014
https://doi.org/10.1109/IWCE.2014.6865878
Maiti CMaiti T(2013)Strain-Engineered MOSFETsStrain-Engineered MOSFETs10.1201/b13014-6(115-142)Online publication date: 3-Jan-2013
https://doi.org/10.1201/b13014-6
Xue JDeng YYe ZWang HYang LYu Z(2012)A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210237420:3(498-511)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1109/TVLSI.2010.2102374
Ghaida RGupta P(2012)DREIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219247731:9(1379-1392)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2192477
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