Cited By
View all- Chauhan PGoyal DHasteer GMathur ASharma N(2009)Non-cycle-accurate sequential equivalence checkingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630033(460-465)Online publication date: 26-Jul-2009
This paper presents a survey of the state-of-art of formal verification technique. The expression models for formal verification are introduced and analyzed. The characteristics of each model are expounded. Moreover, the typical model checking ...
The functional verification of a digital design is an expensive step in the design process. As designs become more complex, simulation is challenged throughout the design and verification process, both at the low level (implementation verification), to ...
A formal verifier is an automated decision procedure that can prove or disprove a set of statements in some logical system of reasoning. Problems informal verification have been posed and studied in a variety of disciplines for many years. However the ...
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