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Construction of concrete verification models from C++

Published: 08 June 2008 Publication History
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  • Abstract

    C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The challenge of using C++ for sequential equivalence checking comes from two aspects (1) Language constructs such as pointers, polymorphism, virtual methods, dynamic memory allocation, dynamic loop bounds, floating points pose difficulty in creating a model suitable for equivalence checking (2) The memory and runtime required for creating models suitable for equivalence checking from practical C++ designs is huge.
    In this paper we describe techniques for constructing verification models from C++ designs containing a very rich set of language constructs. The flow is built keeping in mind that formal methods are inherently capacity constrained but need to be applied to large C++ designs to have practical value.

    References

    [1]
    T. Ball, R. Majumdar, T. Millstein, and S. K. Rajamani. Automatic Predicate Abstraction of C Programs. In Conference on Programming Language Design and Implementation, pages 203--213, 2001.
    [2]
    L. Semeria, Koichi Sato, and G. De Micheli. Synthesis of Hardware Models in C With Pointers and Complex Data Structures. IEEE Transaction on VLSI, 9(6), December 2001.
    [3]
    S. H. Yong and S. Horwitz. Pointer Range Analysis. In Intl. Static Analysis Symposium, pages 133--148, 2004.
    [4]
    E. Clarke, D. Kroening, and K. Yorav. Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking. In Design Automation Conference, pages 368--371, 2003.
    [5]
    A. Chou Y. Xie and D. Engler. ARCHER: Using Symbolic, Path-senstive Analysis to Detect Memory Access Errors. In 11th ACM SIGSOFT Intl. Symp. on Foundations of Software Engineering, pages 327--336, 2003.
    [6]
    A. Koelbl and C. Pixley. Constructing efficient formal models from high-level descriptions using symbolic simulation. Intl. Journal of Parallel Programming, 33(6): 645--666, 2005.
    [7]
    Virtual method table. http://en.wikipedia.org/wiki/Virtualtable.
    [8]
    J. Hauser. Softfloat. http://www.jhauser.us/arithmetic/SoftFloat.html.

    Cited By

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    • (2009)Non-cycle-accurate sequential equivalence checkingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630033(460-465)Online publication date: 26-Jul-2009

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    1. Construction of concrete verification models from C++

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      cover image ACM Conferences
      DAC '08: Proceedings of the 45th annual Design Automation Conference
      June 2008
      993 pages
      ISBN:9781605581156
      DOI:10.1145/1391469
      • General Chair:
      • Limor Fix
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 08 June 2008

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      Author Tags

      1. C++
      2. dynamic memory allocation
      3. equivalence checking
      4. formal verification
      5. pointers

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      • (2009)Non-cycle-accurate sequential equivalence checkingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630033(460-465)Online publication date: 26-Jul-2009

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