research-article

Analyzing static and dynamic write margin for nanometer SRAMs

Authors:

Jiajing Wang,

Satyanand Nalam,

Benton H. CalhounAuthors Info & Claims

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Pages 129 - 134

https://doi.org/10.1145/1393921.1393954

Published: 11 August 2008 Publication History

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Abstract

This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCC_min estimation for active V_DD scaling designs.

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Krishnakant Rai SSahu C(2024)Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power GatingInternational Journal of Innovative Science and Research Technology (IJISRT)10.38124/ijisrt/IJISRT24SEP1230(1578-1584)Online publication date: 1-Oct-2024
https://doi.org/10.38124/ijisrt/IJISRT24SEP1230
Grudanov O(2024)Low-Power 8T Memory Cell of Register File for 180 nm TechnologyRadioelectronics and Communications Systems10.3103/S073527272310005966:12(658-666)Online publication date: 2-Dec-2024
https://doi.org/10.3103/S0735272723100059
Zhou CZhang YZhao YWang Z(2024)A New 8T SRAM Cell Design of Low-Power and High-Write-Speed2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET)10.1109/ISSET62871.2024.10779965(473-476)Online publication date: 23-Aug-2024
https://doi.org/10.1109/ISSET62871.2024.10779965
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Index Terms

Analyzing static and dynamic write margin for nanometer SRAMs
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Static memory

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Published In

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

August 2008

396 pages

ISBN:9781605581095

DOI:10.1145/1393921

General Chairs:
Vijaykrishnan Narayanan
Penn State University
,
C. P. Ravikumar
Texas Instruments
,
Joerg Henkel
Univeristy of Karlsruhe
,
Ali Keshavarzi
Intel Corporation
,
Program Chairs:
Vojin G. Oklobdzija
University of Texas at Dallas
,
Barry Pangrle
Pangrle Consulting

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Published: 11 August 2008

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ISLPED08: International Symposium on Low Power Electronics and Design

August 11 - 13, 2008

Bangalore, India

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Krishnakant Rai SSahu C(2024)Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power GatingInternational Journal of Innovative Science and Research Technology (IJISRT)10.38124/ijisrt/IJISRT24SEP1230(1578-1584)Online publication date: 1-Oct-2024
https://doi.org/10.38124/ijisrt/IJISRT24SEP1230
Grudanov O(2024)Low-Power 8T Memory Cell of Register File for 180 nm TechnologyRadioelectronics and Communications Systems10.3103/S073527272310005966:12(658-666)Online publication date: 2-Dec-2024
https://doi.org/10.3103/S0735272723100059
Zhou CZhang YZhao YWang Z(2024)A New 8T SRAM Cell Design of Low-Power and High-Write-Speed2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET)10.1109/ISSET62871.2024.10779965(473-476)Online publication date: 23-Aug-2024
https://doi.org/10.1109/ISSET62871.2024.10779965
Jung HChang JJeon J(2024)Evaluation of various phase-transition materials for steep switching super-low power application in the latest technology nodeResults in Physics10.1016/j.rinp.2024.10761960(107619)Online publication date: May-2024
https://doi.org/10.1016/j.rinp.2024.107619
Zhao SZhao QHao LPeng CWang YLu WLin ZWu X(2024)Design of polarity hardening SRAM for mitigating single event multiple node upsetsMicroelectronics Journal10.1016/j.mejo.2024.106214149:COnline publication date: 1-Jul-2024
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Pandey MIslam A(2024)Circuit-level design of radiation tolerant memory cellAEU - International Journal of Electronics and Communications10.1016/j.aeue.2023.155103175(155103)Online publication date: Feb-2024
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Liu HCatthoor FLiu HCatthoor F(2024)Extended Write Margin Methodology for SRAM Subarray in Resistance-Dominated Technology NodeCircuit-Technology Co-Optimization of SRAM Design in Advanced CMOS Nodes10.1007/978-3-031-76109-6_3(57-76)Online publication date: 21-Dec-2024
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Kumar TCacho FRoy TDe La Bardonnie MPelle SGiner F(2023)Analytical Model of SRAM VMin to Predict Reliability and Process Impact2023 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW59383.2023.10477717(1-4)Online publication date: 8-Oct-2023
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SRAM read/write margin enhancements using FinFETs

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SRAM read/write margin enhancements using FinFETs

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

SRAM write-ability improvement with transient negative bit-line voltage

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