research-article

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Authors:

Houman Homayoun,

Mohammad Makhzan,

Alex VeidenbaumAuthors Info & Claims

CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems

Pages 197 - 206

https://doi.org/10.1145/1450095.1450125

Published: 19 October 2008 Publication History

Abstract

This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral circuits, which according to recent studies account for a considerable amount of cache leakage. At circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide "when and how" to use these different low-leakage modes using cache miss information to guide its action. This control is based on simple state machines that do not impact area or power consumption and can thus be used even in the resource constrained processors. Experimental results indicate that proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for 65nm technology. The DL1 cache energy-delay product is reduced, on average, by 20%.

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Cited By

Wang HLi WQi WTang DHuang LTang H(2020)Runtime Performance Optimization of 3-D Microprocessors in Dark SiliconIEEE Transactions on Computers10.1109/TC.2020.3015711(1-1)Online publication date: 2020
https://doi.org/10.1109/TC.2020.3015711
Neshatpour KBurleson WKhajeh AHomayoun H(2018)Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal DependenceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.278080026:4(778-791)Online publication date: Apr-2018
https://doi.org/10.1109/TVLSI.2017.2780800
Hou CZhao Q(2016)A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep ModesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241482724:2(706-719)Online publication date: Feb-2016
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Index Terms

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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cover image ACM Conferences

CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems

October 2008

274 pages

ISBN:9781605584690

DOI:10.1145/1450095

Program Chair:
Erik Altman
IBM

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 19 October 2008

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ESWEEK 08

Sponsor:

ESWEEK 08: Fourth Embedded Systems Week

October 19 - 24, 2008

GA, Atlanta, USA

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Wang HLi WQi WTang DHuang LTang H(2020)Runtime Performance Optimization of 3-D Microprocessors in Dark SiliconIEEE Transactions on Computers10.1109/TC.2020.3015711(1-1)Online publication date: 2020
https://doi.org/10.1109/TC.2020.3015711
Neshatpour KBurleson WKhajeh AHomayoun H(2018)Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal DependenceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.278080026:4(778-791)Online publication date: Apr-2018
https://doi.org/10.1109/TVLSI.2017.2780800
Hou CZhao Q(2016)A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep ModesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241482724:2(706-719)Online publication date: Feb-2016
https://doi.org/10.1109/TVLSI.2015.2414827
Lee SKang KKyung C(2015)Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 CacheIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231179823:3(520-533)Online publication date: Mar-2015
https://doi.org/10.1109/TVLSI.2014.2311798
Lee SKang KJung JKyung C(2014)Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessorsFifteenth International Symposium on Quality Electronic Design10.1109/ISQED.2014.6783325(197-204)Online publication date: Mar-2014
https://doi.org/10.1109/ISQED.2014.6783325
Kang KDe Micheli GLee SKyung C(2014)Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cacheFifteenth International Symposium on Quality Electronic Design10.1109/ISQED.2014.6783320(163-170)Online publication date: Mar-2014
https://doi.org/10.1109/ISQED.2014.6783320
Peserico E(2013)Elastic pagingACM SIGMETRICS Performance Evaluation Review10.1145/2494232.247978141:1(349-350)Online publication date: 17-Jun-2013
https://dl.acm.org/doi/10.1145/2494232.2479781
Peserico EHarchol-Balter MDouceur JXu J(2013)Elastic pagingProceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems10.1145/2465529.2479781(349-350)Online publication date: 17-Jun-2013
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Jongpil Jung Kyungsu Kang De Micheli GChong-Min Kyung (2013)Runtime 3-D stacked cache management for chip-multiprocessorsInternational Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2013.6523592(68-72)Online publication date: Mar-2013
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Sasan AAmiri KHomayoun HEltawil AKurdahi F(2012)Variation trained drowsy cache (VTD-Cache)IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.210652320:4(630-642)Online publication date: 1-Apr-2012
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