research-article

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

Authors:

Chris Hyung-il Kim,

Saibal Mukhopadhyay,

Kaushik RoyAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 3

Pages 349 - 357

https://doi.org/10.1109/TVLSI.2004.842903

Published: 01 March 2005 Publication History

Abstract

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.

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Niaraki Asli RTaghipour S(2017)A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET TechnologyJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5659-833:4(449-462)Online publication date: 1-Aug-2017
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Aziz AGupta S(2016)Hybrid Multiplexing (HYM) for Read- and Area-Optimized MRAMs With Separate Read-Write PathsIEEE Transactions on Nanotechnology10.1109/TNANO.2016.254486015:3(473-483)Online publication date: 6-May-2016
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A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 13, Issue 3

March 2005

114 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2005.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 2005

Revised: 23 March 2004

Received: 24 October 2003

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Cited By

Choi IYeung D(2017)Multi-cache resizing via greedy coordinate descentThe Journal of Supercomputing10.1007/s11227-016-1927-073:6(2402-2429)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s11227-016-1927-0
Niaraki Asli RTaghipour S(2017)A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET TechnologyJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5659-833:4(449-462)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1007/s10836-017-5659-8
Aziz AGupta S(2016)Hybrid Multiplexing (HYM) for Read- and Area-Optimized MRAMs With Separate Read-Write PathsIEEE Transactions on Nanotechnology10.1109/TNANO.2016.254486015:3(473-483)Online publication date: 6-May-2016
https://dl.acm.org/doi/10.1109/TNANO.2016.2544860
Wang JWang LYin HWei ZYang ZGong N(2016)cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory SystemIEEE Transactions on Computers10.1109/TC.2014.237518765:4(1055-1067)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1109/TC.2014.2375187
Goud AVenkatesan RRaghunathan ARoy KNebel WAtienza D(2015)Asymmetric underlapped FinFET based robust SRAM design at 7nm nodeProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755905(659-664)Online publication date: 9-Mar-2015
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Corsonello PFrustaci FPerri S(2015)Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI TechnologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.238400723:12(3133-3137)Online publication date: 20-Nov-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2384007
Zang WGordon-Ross A(2013)A survey on cache tuning from a power/energy perspectiveACM Computing Surveys10.1145/2480741.248074945:3(1-49)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2480741.2480749
Sun ZBi XLi HShanbhag NPoncino MChou PAmerasekera A(2012)Process variation aware data management for STT-RAM cache designProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333706(179-184)Online publication date: 30-Jul-2012
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Sun ZBi XLi HWong WOng ZZhu XWu WGaluzzi CCarro LMoshovos APrvulovic M(2011)Multi retention level STT-RAM cache designs with a dynamic refresh schemeProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155659(329-338)Online publication date: 3-Dec-2011
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Homayoun HSasan AGupta AVeidenbaum AKurdahi FDutt NAmato NFranke HKelly P(2010)Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor unitsProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787339(297-308)Online publication date: 17-May-2010
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