Article

A forward body-biased low-leakage SRAM cache: device and architecture considerations

Authors:

Saibal Mukhopadhyay,

Kaushik RoyAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 6 - 9

https://doi.org/10.1145/871506.871511

Published: 25 August 2003 Publication History

Abstract

This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high VT (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieve by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high VT device, the 2-D halo doping profile was optimized considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.

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Cited By

Agarwal SKapoor H(2019)Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management TechniquesVLSI-SoC: Opportunities and Challenges Beyond the Internet of Things10.1007/978-3-030-15663-3_3(46-71)Online publication date: 17-May-2019
https://doi.org/10.1007/978-3-030-15663-3_3
Rezaeizadeh Rookerd RSadeghi-Kohan SNavabi ZChen DHomayoun HTaskin B(2018)Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache ArchitectureProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194599(33-38)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194599
Bikki PKaruppanan P(2017)SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A SurveyCircuits and Systems10.4236/cs.2017.8200308:02(23-52)Online publication date: 2017
https://doi.org/10.4236/cs.2017.82003
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Index Terms

A forward body-biased low-leakage SRAM cache: device and architecture considerations
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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cover image ACM Conferences

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 25 August 2003

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ISLPED03

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

Acceptance Rates

ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Agarwal SKapoor H(2019)Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management TechniquesVLSI-SoC: Opportunities and Challenges Beyond the Internet of Things10.1007/978-3-030-15663-3_3(46-71)Online publication date: 17-May-2019
https://doi.org/10.1007/978-3-030-15663-3_3
Rezaeizadeh Rookerd RSadeghi-Kohan SNavabi ZChen DHomayoun HTaskin B(2018)Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache ArchitectureProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194599(33-38)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194599
Bikki PKaruppanan P(2017)SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A SurveyCircuits and Systems10.4236/cs.2017.8200308:02(23-52)Online publication date: 2017
https://doi.org/10.4236/cs.2017.82003
Azad ZFarbeh HMonazzah AMiremadi S(2017)An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core ProcessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262874228:6(1564-1577)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2628742
Niaraki Asli RTaghipour S(2017)A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET TechnologyJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5659-833:4(449-462)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1007/s10836-017-5659-8
Jokar MArjomand MSarbazi-Azad H(2016)SequoiaIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.242095424:3(954-967)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2420954
Kotra JArjomand MGuttman DKandemir MDas C(2016)Re-NUCA: A Practical NUCA Architecture for ReRAM Based Last-Level Caches2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS.2016.79(576-585)Online publication date: May-2016
https://doi.org/10.1109/IPDPS.2016.79
Yarmand REbrahimi BAfzali-Kusha HAfzali-Kusha APedram M(2015)High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistorsSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085371(10-17)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085371
Ansari MAfzali-Kusha HEbrahimi BNavabi ZAfzali-Kusha APedram M(2015)A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologiesIntegration, the VLSI Journal10.1016/j.vlsi.2015.02.00250:C(91-106)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2015.02.002
Wang JDong XXie Y(2014)Preventing STT-RAM Last-Level Caches from Port ObstructionACM Transactions on Architecture and Code Optimization10.1145/263304611:3(1-19)Online publication date: 31-Jul-2014
https://dl.acm.org/doi/10.1145/2633046
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