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- Kumar M and Venkateshrao D A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design Proceedings of the 16th International Conference on VLSI Design
- Narendra S, De V, Borkar S, Antoniadis D and Chandrakasan A Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS Proceedings of the 2002 international symposium on Low power electronics and design, (19-23)
- Taur Y (2002). CMOS design near the limit of scaling, IBM Journal of Research and Development, 46:2-3, (213-222), Online publication date: 1-Mar-2002.
- Mandelman J, Dennard R, Bronner G, DeBrosse J, Divakaruni R, Li Y and Radens C (2002). Challenges and future directions for the scaling of dynamic random-access memory (DRAM), IBM Journal of Research and Development, 46:2-3, (187-212), Online publication date: 1-Mar-2002.
- Ning T (2002). Why BiCMOS and SOI BiCMOS?, IBM Journal of Research and Development, 46:2-3, (181-186), Online publication date: 1-Mar-2002.
- Shahidi G (2002). SOI technology for the GHz era, IBM Journal of Research and Development, 46:2-3, (121-131), Online publication date: 1-Mar-2002.
- Kao J, Narendra S and Chandrakasan A Subthreshold leakage modeling and reduction techniques Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (141-148)
- Im H Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model) Proceedings of the 2002 international symposium on Low power electronics and design, (13-18)
- Im H, Inukai T, Gomyo H, Hiramoto T and Sakurai T VTCMOS characteristics and its optimum conditions predicted by a compact analytical model Proceedings of the 2001 international symposium on Low power electronics and design, (123-128)
- Kosonocky S, Immediato M, Cottrell P, Hook T, Mann R and Brown J Enchanced multi-threshold (MTCMOS) circuits using variable well bias Proceedings of the 2001 international symposium on Low power electronics and design, (165-169)
- Zhang R, Roy K and Janes D Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design Proceedings of the 2001 international symposium on Low power electronics and design, (213-218)
- Gutmann P Data remanence in semiconductor devices Proceedings of the 10th conference on USENIX Security Symposium - Volume 10
- Sirisantana N, Cao A, Davidson S, Kok Koh C and Roy K Selectively clocked skewed logic (SCSL) Proceedings of the 2001 international symposium on Low power electronics and design, (267-270)
- Nose K and Sakurai T Optimization of VDD and VTH for low-power and high speed applications Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (469-474)
- High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
- Tsang J, Kash J and Vallett D (2000). Picosecond imaging circuit analysis, IBM Journal of Research and Development, 44:4, (583-603), Online publication date: 1-Jul-2000.
- Buchanan D (1999). Scaling the gate dielectric, IBM Journal of Research and Development, 43:3, (245-264), Online publication date: 1-May-1999.
Index Terms
- Fundamentals of modern VLSI devices
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