Article

Enchanced multi-threshold (MTCMOS) circuits using variable well bias

Authors:

Stephen V. Kosonocky,

Jeff BrownAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 165 - 169

https://doi.org/10.1145/383082.383125

Published: 06 August 2001 Publication History

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References

[1]

Yang, I; Vieri, C; Chandrakasan, A; Antoniadis, D, "Back Gated CMOS on SOIAS for Dynamic Threshold Control", IEEE 1995 IEDM, December 1995.

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Mutoh, S.; Douseki, T.; Matsuya, Y.; Aoki, T.; Shige-matsu, S.;Yamada,"1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS" J. Solid-State Circuits, IEEE Journal of, Volume: 30-8, Aug. 1995.

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Kawaguchi, H; Nose, K; Sakurai T, "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-by Current", J. Solid-State Cir-cuits, IEEE Journal of, Volume: 35-10, Oct. 2000.

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Yuan Taur; Tak. H. Ning, Fundemental of Modern VLSI Devices, Cambridge University Press. Cambridge, 1998.

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Cited By

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Sharroush SAbdalla Y(2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
https://doi.org/10.1016/j.aeue.2021.153882
Angizi SSun JZhang WFan D(2019)AlignSProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317764(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317764
Guz ZLi HShayesteh ABalakrishnan V(2018)Performance Characterization of NVMe-over-Fabrics Storage DisaggregationACM Transactions on Storage10.1145/323956314:4(1-18)Online publication date: 4-Dec-2018
https://dl.acm.org/doi/10.1145/3239563
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Index Terms

Enchanced multi-threshold (MTCMOS) circuits using variable well bias
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Input / output circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01

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SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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https://doi.org/10.1016/j.aeue.2021.153882
Angizi SSun JZhang WFan D(2019)AlignSProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317764(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317764
Guz ZLi HShayesteh ABalakrishnan V(2018)Performance Characterization of NVMe-over-Fabrics Storage DisaggregationACM Transactions on Storage10.1145/323956314:4(1-18)Online publication date: 4-Dec-2018
https://dl.acm.org/doi/10.1145/3239563
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Low power shift register using MTCMOS edge-trigger D flip flop transmission gate in sub-threshold region

Sleep transistor distribution in row-based MTCMOS designs

Design of multi-threshold threshold gate using MOS-NDR circuits suitable for CMOS process