Article

Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations

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Kaushik RoyAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 14 - 19

https://doi.org/10.1145/1077603.1077609

Published: 08 August 2005 Publication History

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Abstract

This paper explores the effectiveness of dual-V_t design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process parameters. The present way of realizing high-V_t devices results in high junction tunneling leakage compared to low-V_t devices, which in turn may result in negligible leakage savings for dual-V_t designs in scaled technologies. Moreover, increase in process variation severely affects the yield of such designs. This paper suggests important measures that need to be incorporated in conventional dual-V_t design to achieve total leakage power improvement while ensuring yield. It also shows that different process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-V_t designs in sub-50nm technologies

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Cited By

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Majzoub S(2015)Reducing random-dopant fluctuation impact using footer transistors in many-core systemsIntegration, the VLSI Journal10.1016/j.vlsi.2014.06.00548:C(46-54)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.06.005
Mande SChandorkar SChandorkar A(2011)Process variation aware dual-Vth assignment technique for low power nanoscale CMOS designMicroelectronics Reliability10.1016/j.microrel.2011.04.01151:12(2357-2365)Online publication date: Dec-2011
https://doi.org/10.1016/j.microrel.2011.04.011
Leinweber LBhunia SSciuto D(2008)Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reductionProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403466(373-378)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403466
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Index Terms

Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Majzoub S(2015)Reducing random-dopant fluctuation impact using footer transistors in many-core systemsIntegration, the VLSI Journal10.1016/j.vlsi.2014.06.00548:C(46-54)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.06.005
Mande SChandorkar SChandorkar A(2011)Process variation aware dual-Vth assignment technique for low power nanoscale CMOS designMicroelectronics Reliability10.1016/j.microrel.2011.04.01151:12(2357-2365)Online publication date: Dec-2011
https://doi.org/10.1016/j.microrel.2011.04.011
Leinweber LBhunia SSciuto D(2008)Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reductionProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403466(373-378)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403466
Leinweber LBhunia S(2008)Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction2008 Design, Automation and Test in Europe10.1109/DATE.2008.4484709(373-378)Online publication date: Mar-2008
https://doi.org/10.1109/DATE.2008.4484709
Agarwal AKang KBhunia SGallagher JRoy K(2007)Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89868315:6(660-671)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898683
Oliver LChakrabarty KMassoud HQu GIsmail YNarayanan VZhou H(2006)An evaluation of the impact of gate oxide tunneling on dual-V-based leakage reduction techniquesProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127935(105-110)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127935
Tzartzanis N(2006)Static Memory DesignHigh-Performance Energy-Efficient Microprocessor Design10.1007/978-0-387-34047-0_4(89-119)Online publication date: 2006
https://doi.org/10.1007/978-0-387-34047-0_4

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Device-aware yield-centric dual-V_t design under parameter variations in nanoscale technologies

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Prediction of leakage power under process uncertainties

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Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Prediction of leakage power under process uncertainties

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