Article

Nanometer device scaling in subthreshold circuits

Authors:

Dennis Sylvester,

David BlaauwAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 700 - 705

https://doi.org/10.1145/1278480.1278656

Published: 04 June 2007 Publication History

Abstract

Subthreshold circuit design is a strong candidate for use in future low power applications. It is not clear, however, that device scaling to 45nm and beyond will be beneficial in Subthreshold circuits. We investigate the implications of device scaling on subthreshold circuits and find that the slow scaling of gate oxide thickness leads to a 60% reduction in I_on/I_off between the 90nm and 32nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-V_th circuits.

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Cited By

Hao Cai Kaikai Liu de Barros Naviner L(2014)Reliability-aware delay faults evaluation of CMOS flip-flops2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)10.1109/MIXDES.2014.6872224(385-389)Online publication date: Jun-2014
https://doi.org/10.1109/MIXDES.2014.6872224
Wang CYe YCao Y(2012)The potential of Fe-FET for robust design under variations: A compact modeling studyMicroelectronics Journal10.1016/j.mejo.2012.05.01243:11(898-903)Online publication date: Nov-2012
https://doi.org/10.1016/j.mejo.2012.05.012
Dhar SPattanaik MRajaram P(2011)Advancement in nanoscale CMOS device design en route to ultra-low-power applicationsVLSI Design10.1155/2011/1785162011(1-19)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/178516
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Index Terms

Nanometer device scaling in subthreshold circuits
1. Hardware
  1. Integrated circuits

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cover image ACM Conferences

DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 04 June 2007

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DAC07: The 44th Annual Design Automation Conference 2007

June 4 - 8, 2007

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DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Hao Cai Kaikai Liu de Barros Naviner L(2014)Reliability-aware delay faults evaluation of CMOS flip-flops2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)10.1109/MIXDES.2014.6872224(385-389)Online publication date: Jun-2014
https://doi.org/10.1109/MIXDES.2014.6872224
Wang CYe YCao Y(2012)The potential of Fe-FET for robust design under variations: A compact modeling studyMicroelectronics Journal10.1016/j.mejo.2012.05.01243:11(898-903)Online publication date: Nov-2012
https://doi.org/10.1016/j.mejo.2012.05.012
Dhar SPattanaik MRajaram P(2011)Advancement in nanoscale CMOS device design en route to ultra-low-power applicationsVLSI Design10.1155/2011/1785162011(1-19)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/178516
Datta BBurleson WAtienza DXie YAyala JStevens K(2011)A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOSProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973037(133-138)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973037
Abouzeid FClerc SFirmin FRenaudin MSas TSicard G(2011)40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036916:3(1-17)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1145/1970353.1970369
Ain APal DDasgupta PMukhopadhyay SMukhopadhyay RGough J(2011)ChassisACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036716:3(1-30)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1145/1970353.1970367
Stitt GVahid F(2011)Thread WarpingACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036516:3(1-21)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1145/1970353.1970365
Liu YHu J(2011)GPU-Based Parallelization for Fast Circuit OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197035716:3(1-14)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1145/1970353.1970357
Han YChakraborty KRoy SKuntamukkala V(2011)Design and Implementation of a Throughput-Optimized GPU Floorplanning AlgorithmACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197035616:3(1-21)Online publication date: 1-Jun-2011
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Ludwin ABetz V(2011)Efficient and Deterministic Parallel Placement for FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197035516:3(1-23)Online publication date: 1-Jun-2011
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