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Instruction-level parallelism in Prolog: analysis and architectural support

Authors:

Alessandro De Gloria,

Paolo FaraboschiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 20, Issue 2

Pages 224 - 233

https://doi.org/10.1145/146628.139730

Published: 01 April 1992 Publication History

Abstract

The demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of prolog. Unlike past microcoded implementation based on the Warren machine model, novel trends in high performance Prolog processors suggest the implementation of RISC-based processors committed to prolog only through the adoption of a few basic dedicated features, like the Berkeley Abstract Machine (BAM) processor.

Following the idea of using a smart compiler for a simple instruction set, the SYMBOL project represents an experiment in applying global compaction techniques and VLIW design philosophy to the static exploitation of instruction-level parallelism in Prolog.

This paper presents code analysis results and shows how we can approach the theoretical speed-up limit (about 3) imposed by Amdahl's law on shared memory models, by means of global code optimizations and a suitable architectural support. In addition, we show implementation details and some preliminary data of a VLSI prototype architecture.

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Cited By

Bellotti FBricco EBruzzone ACaviglia DDi Zitti EGastaldo PGrosso DMagnani LOlivieri MRaggio MValle MVerri ABerta R(2024)Alessandro De Gloria, a Pioneer in Electronic Engineering ApplicationsApplications in Electronics Pervading Industry, Environment and Society10.1007/978-3-031-48121-5_1(3-11)Online publication date: 13-Jan-2024
https://doi.org/10.1007/978-3-031-48121-5_1
Kim HGaudiot J(1994)Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel ArchitecturesProceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques10.5555/647042.713814(225-234)Online publication date: 24-Aug-1994
https://dl.acm.org/doi/10.5555/647042.713814
Ruey-Liang Ma Chung-Ping Chung (1994)Branch prediction for enhancing fine-grained parallelism in PrologProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590462(744-751)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590462
Show More Cited By

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Instruction-level parallelism in Prolog: analysis and architectural support

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 20, Issue 2

Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

May 1992

429 pages

ISSN:0163-5964

DOI:10.1145/146628

Editor:
Allan Gotlieb
New York Univ., New York, NY

Issue’s Table of Contents

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture
May 1992
439 pages
ISBN:0897915097
DOI:10.1145/139669
Chairman:
Allan Gottlieb
New York Unvi., New York, NY

Copyright © 1992 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

Published in SIGARCH Volume 20, Issue 2

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Cited By

Bellotti FBricco EBruzzone ACaviglia DDi Zitti EGastaldo PGrosso DMagnani LOlivieri MRaggio MValle MVerri ABerta R(2024)Alessandro De Gloria, a Pioneer in Electronic Engineering ApplicationsApplications in Electronics Pervading Industry, Environment and Society10.1007/978-3-031-48121-5_1(3-11)Online publication date: 13-Jan-2024
https://doi.org/10.1007/978-3-031-48121-5_1
Kim HGaudiot J(1994)Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel ArchitecturesProceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques10.5555/647042.713814(225-234)Online publication date: 24-Aug-1994
https://dl.acm.org/doi/10.5555/647042.713814
Ruey-Liang Ma Chung-Ping Chung (1994)Branch prediction for enhancing fine-grained parallelism in PrologProceedings of 1994 International Conference on Parallel and Distributed Systems10.1109/ICPADS.1994.590462(744-751)Online publication date: 1994
https://doi.org/10.1109/ICPADS.1994.590462
Costa ADe Gloria AFaraboschi POlivieri MWolfe AMangione-Smith W(1993)An analysis of dynamic scheduling techniques for symbolic applicationsProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255284(185-191)Online publication date: 1-Dec-1993
https://dl.acm.org/doi/10.5555/255235.255284
Rau B(1993)Dynamically scheduled VLIW processorsProceedings of the 26th Annual International Symposium on Microarchitecture10.1109/MICRO.1993.282744(80-92)Online publication date: 1993
https://doi.org/10.1109/MICRO.1993.282744
Baldi LCivera PIurlaro AMasera GPagni APiccinini GPoluzzi RRoch MZamboni M(1993)PROXIMA: PROlog eXecutIon MAchineIEEE Journal of Solid-State Circuits10.1109/4.21000428:3(362-370)Online publication date: Mar-1993
https://doi.org/10.1109/4.210004
De Gloria AFaraboschi POlivieri MGuidetti E(1992)ASIC and board design of a high performance parallel architectureProceedings Euro ASIC '9210.1109/EUASIC.1992.228047(244-249)Online publication date: 1992
https://doi.org/10.1109/EUASIC.1992.228047

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