Article

Free access

Resistance extraction using a routing algorithm

Authors:

Lorenz Ladage,

Rainer LeupersAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 38 - 42

https://doi.org/10.1145/157485.164559

Published: 01 July 1993 Publication History

PDF eReader

References

[1]

Barke, E.: Resistance Calculation from Mask Artwork Data by Finite Element Method, 22nd Design Automation Conference, 1985, pp. 305-311

Digital Library

Google Scholar

[2]

R. Brueck and K. Hahn and L. Ladage and E. Migas and B. Reusch and J. Waterkamp: CAMBIO: How to make cell libraries keep pace with technology evolution, FIP WG 10.5 Workshop, Grenoble, 1992, pp. 97-102

Google Scholar

[3]

Hightower, D.W.: A Solution to the Line-Routing Problem on the Continous Plane, 6th Design Automation Workshop, 1969, pp. 1-24

Digital Library

Google Scholar

[4]

Horowitz, M./Dutton, R.W.: Resistance Extraction from Mask Layout Data, IEEE Transactions on CAD, Vol. CAD-2, No. 3, 1983, pp. 145-150

Google Scholar

[5]

Hwang, J.P.: REX- A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis, 28th Design Automation Conference, 1991, pp. 717-722

Digital Library

Google Scholar

[6]

Lee, C.Y.: An Algorithm for Path Connections and its Applications, IRE Transactions on electronic Computers, Vol. EC- 10, 1961, pp. 346-365

Google Scholar

[7]

Mikami, K./Tabuchi, K." A Computer Program for Optimal Routing of Printed Circuit Connectors, IFIPS Proc., Vol. H47, 1968, pp. 1475-1478

Google Scholar

Cited By

View all

P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Computer-Aided Design of Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_21(333-359)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_21
Roberts RFourie C(2014)Layout-versus-schematic verification for superconductive integrated circuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2014.2373035(1-1)Online publication date: 2014
https://doi.org/10.1109/TASC.2014.2373035
Jerke GLienig JScheible JMalik SFix LKahng A(2004)Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designsProceedings of the 41st annual Design Automation Conference10.1145/996566.996618(181-184)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996618
Show More Cited By

Index Terms

Resistance extraction using a routing algorithm
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Routing and network design problems

Recommendations

Deadlock-Free Routing in Irregular Networks Using Prefix Routing Algorithm
OPPRES: Opportunistic Routing algorithm for routing messages in emergency situations using vehicular delay tolerant network
2016 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS)
A vehicular delay tolerant network (VDTN) is a special type of delay tolerant network (DTN), in which vehicles act as mobile nodes that are carriers of the message. It is characterized by the absence of an end-to-end connectivity between the nodes ...
A routing optimization algorithm for BGP egress selection
ICDCIT'06: Proceedings of the Third international conference on Distributed Computing and Internet Technology

BGP optimal egress selection is one of a recent trend in routing research. Current hot-potato routing has the problem of routing instability. This paper provides a new algorithm named BGP-RO-ES to minimize hot-potato disruptions while satisfying ...

Comments

Information & Contributors

Information

Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC93

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
407
Total Downloads

Downloads (Last 12 months)80
Downloads (Last 6 weeks)15

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Computer-Aided Design of Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_21(333-359)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_21
Roberts RFourie C(2014)Layout-versus-schematic verification for superconductive integrated circuitsIEEE Transactions on Applied Superconductivity10.1109/TASC.2014.2373035(1-1)Online publication date: 2014
https://doi.org/10.1109/TASC.2014.2373035
Jerke GLienig JScheible JMalik SFix LKahng A(2004)Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designsProceedings of the 41st annual Design Automation Conference10.1145/996566.996618(181-184)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996618
Li HCarballido JYu HOkhmatovski VRosenbaum ECangellaris APileggi LKuehlmann A(2002)Comprehensive frequency-dependent substrate noise analysis using boundary element methodsProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774573(2-9)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774573
Hongmei Li Carballido JYu HOkhmatovski VRosenbaum ECangellaris A(2002)Comprehensive frequency-dependent substrate noise analysis using boundary element methodsIEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.10.1109/ICCAD.2002.1167506(2-9)Online publication date: 2002
https://doi.org/10.1109/ICCAD.2002.1167506
Li QKang S(2001)Trapezoid-to-simple polygon recomposition for resistance extractionISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)10.1109/ISCAS.2001.922093(495-498)Online publication date: 2001
https://doi.org/10.1109/ISCAS.2001.922093
Yucheng Wang Overhauser DBasel M(1995)Accurate parasitic resistance extraction for interconnection analysisProceedings of the IEEE 1995 Custom Integrated Circuits Conference10.1109/CICC.1995.518180(255-258)Online publication date: 1995
https://doi.org/10.1109/CICC.1995.518180

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Deadlock-Free Routing in Irregular Networks Using Prefix Routing Algorithm

OPPRES: Opportunistic Routing algorithm for routing messages in emergency situations using vehicular delay tolerant network

A routing optimization algorithm for BGP egress selection

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Deadlock-Free Routing in Irregular Networks Using Prefix Routing Algorithm

OPPRES: Opportunistic Routing algorithm for routing messages in emergency situations using vehicular delay tolerant network

A routing optimization algorithm for BGP egress selection

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Share

Share this Publication link

Share on social media

Affiliations