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An architectural transformation program for optimization of digital systems by multi-level decomposition

Authors:

Abhijit Chatterjee,

Rabindra K. RoyAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 343 - 348

https://doi.org/10.1145/157485.164923

Published: 01 July 1993 Publication History

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Vijay S(2009)Low-complexity implementation of state-space structures in linear DSP synthesis2009 52nd IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2009.5236022(594-597)Online publication date: Aug-2009
https://doi.org/10.1109/MWSCAS.2009.5236022
Potkonjak MSrivastava MChandrakasan A(2006)Multiple constant multiplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48666215:2(151-165)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.486662
Xin Zhang Jie Chen Xiaoxu Guo Baofeng Li (2003)Low power and concurrency optimization of the computational unit for DSP processors based on software2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-0310.1109/ICASIC.2003.1277577(424-427 Vol.1)Online publication date: 2003
https://doi.org/10.1109/ICASIC.2003.1277577
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An architectural transformation program for optimization of digital systems by multi-level decomposition

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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

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Cited By

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Vijay S(2009)Low-complexity implementation of state-space structures in linear DSP synthesis2009 52nd IEEE International Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2009.5236022(594-597)Online publication date: Aug-2009
https://doi.org/10.1109/MWSCAS.2009.5236022
Potkonjak MSrivastava MChandrakasan A(2006)Multiple constant multiplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48666215:2(151-165)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.486662
Xin Zhang Jie Chen Xiaoxu Guo Baofeng Li (2003)Low power and concurrency optimization of the computational unit for DSP processors based on software2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-0310.1109/ICASIC.2003.1277577(424-427 Vol.1)Online publication date: 2003
https://doi.org/10.1109/ICASIC.2003.1277577
Hu AAl-Khalili A(2002)Comparison of constant coefficient multipliers for CSD and Booth recodingThe 14th International Conference on Microelectronics,10.1109/ICM-02.2002.1161498(66-69)Online publication date: 2002
https://doi.org/10.1109/ICM-02.2002.1161498
Nguyen HChatterjee A(2000)Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.8636218:4(419-424)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1109/92.863621
Nguyen HChatterjee ARoy R(1998)Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP SynthesisJournal of VLSI Signal Processing Systems10.1023/A:100793720927618:1(25-38)Online publication date: 1-Jan-1998
https://dl.acm.org/doi/10.1023/A%3A1007937209276
Matsuura AYukishita MNagoya A(1997)An efficient hierarchical clustering method for the multiple constant multiplication problemProceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1997.600064(83-88)Online publication date: 1997
https://doi.org/10.1109/ASPDAC.1997.600064
Nguyen HChatterjee A(1996)Activity measures for fast relative power estimation directed numerical transformation for low power DSP synthesis1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 9610.1109/ISCAS.1996.541890(17-20)Online publication date: 1996
https://doi.org/10.1109/ISCAS.1996.541890
Hartley R(1996)Subexpression sharing in filters using canonic signed digit multipliersIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing10.1109/82.53900043:10(677-688)Online publication date: Jan-1996
https://doi.org/10.1109/82.539000
Huy Nguyen Chatterjee A(1995)OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositionsProceedings Sixteenth Conference on Advanced Research in VLSI10.1109/ARVLSI.1995.515625(258-271)Online publication date: 1995
https://doi.org/10.1109/ARVLSI.1995.515625
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