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The implementation of an SVP many-core processor and the evaluation of its memory architecture

Authors:

Chris Jesshope,

Mike Lankamp,

Li ZhangAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 37, Issue 2

Pages 38 - 45

https://doi.org/10.1145/1577129.1577136

Published: 23 July 2009 Publication History

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Abstract

Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of silicon technology. This paper presents a many-core processor that supports an abstract model of concurrency, based on a Self-adaptive Virtual Processor (SVP). This processor implements instructions, which automatically map and schedule threads providing a code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this processor architecture is the memory system. This paper briefly presents the model and evaluates its memory architecture.

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Cited By

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Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Uddin I(2015)High-level simulation of concurrency operations in microthreaded many-core architecturesGSTF Journal on Computing (JoC)10.7603/s40601-014-0021-94:3Online publication date: 13-Dec-2015
https://doi.org/10.7603/s40601-014-0021-9
Mastoras AManis G(2015)Ariadne - Directive-based parallelism extraction from recursive functionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.07.00986:C(16-28)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.jpdc.2015.07.009
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The implementation of an SVP many-core processor and the evaluation of its memory architecture

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 37, Issue 2

May 2009

69 pages

ISSN:0163-5964

DOI:10.1145/1577129

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Association for Computing Machinery

New York, NY, United States

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Published: 23 July 2009

Published in SIGARCH Volume 37, Issue 2

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Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Uddin I(2015)High-level simulation of concurrency operations in microthreaded many-core architecturesGSTF Journal on Computing (JoC)10.7603/s40601-014-0021-94:3Online publication date: 13-Dec-2015
https://doi.org/10.7603/s40601-014-0021-9
Mastoras AManis G(2015)Ariadne - Directive-based parallelism extraction from recursive functionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.07.00986:C(16-28)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.jpdc.2015.07.009
Uddin IPoss RJesshope C(2014)Analytical-Based High-Level Simulation of the Microthreaded Many-Core ArchitecturesProceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2014.81(344-351)Online publication date: 12-Feb-2014
https://dl.acm.org/doi/10.1109/PDP.2014.81
Uddin IPoss RJesshope C(2014)Cache-based high-level simulation of microthreaded many-core architecturesJournal of Systems Architecture10.1016/j.sysarc.2014.05.00360:7(529-552)Online publication date: Aug-2014
https://doi.org/10.1016/j.sysarc.2014.05.003
Poss RLankamp MYang QFu JVan Tol MUddin IJesshope C(2013)Apple-COREMicroprocessors & Microsystems10.1016/j.micpro.2013.05.00437:8(1090-1101)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1016/j.micpro.2013.05.004
van der Veldt Kvan Nieuwpoort RVarbanescu AJesshope CVarbanescu Avan Nieuwpoort RZwart SVarbanescu A(2012)A polyphase filter for GPUs and multi-core processorsProceedings of the 2012 workshop on High-Performance Computing for Astronomy Date10.1145/2286976.2286986(33-40)Online publication date: 18-Jun-2012
https://dl.acm.org/doi/10.1145/2286976.2286986
Uddin MJesshope Cvan Tol MPoss RPérez DNiar SSilvano CAbhari M(2012)Collecting signatures to model latency tolerance in high-level simulations of microthreaded coresProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162132(1-8)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162132
Lihan Ju Ping Pan Baixing Quan Tianzhou Chen Minghui Wu (2012)Block-based hardware scheduler design on Many-core architecture2012 IEEE International Symposium on Industrial Electronics10.1109/ISIE.2012.6237193(814-819)Online publication date: May-2012
https://doi.org/10.1109/ISIE.2012.6237193
UDDIN MVAN TOL MJESSHOPE C(2011)HIGH LEVEL SIMULATION OF SVP MANY-CORE SYSTEMSParallel Processing Letters10.1142/S012962641100030821:04(413-438)Online publication date: Dec-2011
https://doi.org/10.1142/S0129626411000308
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Threaded Dynamic Memory Management in Many-Core Processors

The Superthreaded Processor Architecture

An Architecture of On-Chip-Memory Multi-threading Processor

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Threaded Dynamic Memory Management in Many-Core Processors

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An Architecture of On-Chip-Memory Multi-threading Processor

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