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A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints

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Peng LiuAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 7, Issue 1

Article No.: 1, Pages 1 - 30

https://doi.org/10.1145/1736065.1736066

Published: 07 May 2010 Publication History

Abstract

In this article, we investigate the Intellectual Property (IP) mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture such that the power consumption due to intercore communications is minimized. This IP mapping problem is considered under both bandwidth and latency constraints as imposed by the applications and the on-chip network infrastructure. By examining various applications' communication characteristics extracted from their respective communication trace graphs, two distinguishable connectivity templates are realized: the graphs with tightly coupled vertices and those with distributed vertices. These two templates are formally defined in this article, and different mapping heuristics are subsequently developed to map them. In general, tightly coupled vertices are mapped onto tiles that are physically close to each other while the distributed vertices are mapped following a graph partition scheme. Experimental results on both random and multimedia benchmarks have confirmed that the proposed template-based mapping algorithm achieves an average of 15% power savings as compared with MOCA, a fast greedy-based mapping algorithm. Compared with a branch-and-bound--based mapping algorithm, which produces near optimal results but incurs an extremely high computation cost, the proposed algorithm, due to its polynomial runtime complexity, can generate the results of almost the same quality with much less CPU time. As the on-chip network size increases, the superiority of the proposed algorithm becomes more evident.

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Cited By

Chen QHuang WZhang YHuang Y(2021)An IP Core Mapping Algorithm Based on Neural NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.303365829:1(189-202)Online publication date: Jan-2021
https://doi.org/10.1109/TVLSI.2020.3033658
YOKOTA TOOTSU KOHKAWA T(2020)Genetic Node-Mapping Methods for Rapid Collective CommunicationsIEICE Transactions on Information and Systems10.1587/transinf.2018EDP7386E103.D:1(111-129)Online publication date: 1-Jan-2020
https://doi.org/10.1587/transinf.2018EDP7386
Sharma PBiswas SMitra P(2019)Energy efficient heuristic application mapping for 2-D mesh-based network-on-chipMicroprocessors and Microsystems10.1016/j.micpro.2018.10.00864(88-100)Online publication date: Feb-2019
https://doi.org/10.1016/j.micpro.2018.10.008
Show More Cited By

Index Terms

A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
1. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints
2. Networks
  1. Network architectures

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 7, Issue 1

April 2010

151 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/1736065

Issue’s Table of Contents

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 07 May 2010

Accepted: 01 September 2009

Revised: 01 July 2009

Received: 01 March 2009

Published in TACO Volume 7, Issue 1

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Cited By

Chen QHuang WZhang YHuang Y(2021)An IP Core Mapping Algorithm Based on Neural NetworksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.303365829:1(189-202)Online publication date: Jan-2021
https://doi.org/10.1109/TVLSI.2020.3033658
YOKOTA TOOTSU KOHKAWA T(2020)Genetic Node-Mapping Methods for Rapid Collective CommunicationsIEICE Transactions on Information and Systems10.1587/transinf.2018EDP7386E103.D:1(111-129)Online publication date: 1-Jan-2020
https://doi.org/10.1587/transinf.2018EDP7386
Sharma PBiswas SMitra P(2019)Energy efficient heuristic application mapping for 2-D mesh-based network-on-chipMicroprocessors and Microsystems10.1016/j.micpro.2018.10.00864(88-100)Online publication date: Feb-2019
https://doi.org/10.1016/j.micpro.2018.10.008
Agyeman MAhmadinia ABagherzadeh N(2018)Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chipJournal of Systems Architecture10.1016/j.sysarc.2018.08.00289(103-117)Online publication date: Sep-2018
https://doi.org/10.1016/j.sysarc.2018.08.002
Hoveida MAghaaliakbari FJalili MBashizade RArjomand MSarbazi-Azad H(2018)Revisiting Processor Allocation and Application Mapping in Future CMPs in Dark Silicon EraDark Silicon and Future On-chip Systems10.1016/bs.adcom.2018.04.001(35-81)Online publication date: 2018
https://doi.org/10.1016/bs.adcom.2018.04.001
Hoveida MAghaaliakbari FBashizade RArjomand MSarbazi-Azad H(2017)Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon EraACM Transactions on Design Automation of Electronic Systems10.1145/305520222:4(1-26)Online publication date: 15-Jun-2017
https://dl.acm.org/doi/10.1145/3055202
Soumya JBabu KChattopadhyay S(2017)Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip ArchitectureJournal of Circuits, Systems and Computers10.1142/S021812661750174226:11(1750174)Online publication date: Nov-2017
https://doi.org/10.1142/S0218126617501742
Pang KFresse VYao S(2016)Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chipThe Journal of Supercomputing10.1007/s11227-016-1732-972:6(2283-2309)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1007/s11227-016-1732-9
Benhaoua MSingh A(2015)Dynamic communications mapping in multi-tasks NoC-based heterogeneous MPSoCs platformInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2015.0728565:4(240-251)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1504/IJHPSA.2015.072856
Khawaja SMushtaq MKhan SAkram MJamal H(2015)Designing Area Optimized Application-Specific Network-On-Chip Architectures while Providing Hard QoS GuaranteesPLOS ONE10.1371/journal.pone.012523010:4(e0125230)Online publication date: 21-Apr-2015
https://doi.org/10.1371/journal.pone.0125230
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