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RNFTL: a reuse-aware NAND flash translation layer for flash memory

Published: 13 April 2010 Publication History

Abstract

In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a merge operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

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Cited By

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  • (2020)MNFTLACM Transactions on Design Automation of Electronic Systems10.1145/339803725:6(1-19)Online publication date: 12-Aug-2020
  • (2019)A Novel Independent Channel Addressing Flash Translation Layer Scheme2019 IEEE 3rd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)10.1109/ITNEC.2019.8729164(1047-1051)Online publication date: Mar-2019
  • (2018)A space reuse strategy for flash translation layers in SLC NAND flash memory storage systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.214201520:6(1094-1107)Online publication date: 29-Dec-2018
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Published In

cover image ACM Conferences
LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
April 2010
184 pages
ISBN:9781605589534
DOI:10.1145/1755888
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 45, Issue 4
    LCTES '10
    April 2010
    170 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1755951
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 April 2010

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Author Tags

  1. endurance
  2. flash memory
  3. reuse
  4. space utilization
  5. wear-leveling

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LCTES '10

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

View all
  • (2020)MNFTLACM Transactions on Design Automation of Electronic Systems10.1145/339803725:6(1-19)Online publication date: 12-Aug-2020
  • (2019)A Novel Independent Channel Addressing Flash Translation Layer Scheme2019 IEEE 3rd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)10.1109/ITNEC.2019.8729164(1047-1051)Online publication date: Mar-2019
  • (2018)A space reuse strategy for flash translation layers in SLC NAND flash memory storage systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.214201520:6(1094-1107)Online publication date: 29-Dec-2018
  • (2018)MaCACHJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.03.00161:3(157-171)Online publication date: 29-Dec-2018
  • (2017)On Space Utilization Enhancement of File Systems for Embedded Storage SystemsACM Transactions on Embedded Computing Systems10.1145/282048816:3(1-28)Online publication date: 11-Apr-2017
  • (2017)Software Support Inside and Outside Solid-State Devices for High Performance and High EfficiencyProceedings of the IEEE10.1109/JPROC.2017.2679490105:9(1650-1665)Online publication date: Sep-2017
  • (2017)DA-FTL: Dynamic associative flash translation layer2017 19th International Symposium on Computer Architecture and Digital Systems (CADS)10.1109/CADS.2017.8310682(1-5)Online publication date: Dec-2017
  • (2016)NVRAM-Assisted Optimization Techniques for Flash Memory Management in Embedded Sensor NodesSmart Sensors and Systems10.1007/978-3-319-33201-7_6(135-153)Online publication date: 17-Oct-2016
  • (2015)Adaptive Wear-Leveling in Flash-Based MemoryIEEE Computer Architecture Letters10.1109/LCA.2014.232987114:1(1-4)Online publication date: 1-Jan-2015
  • (2015)SmartBackupProceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and Systems10.1109/HPCC-CSS-ICESS.2015.180(746-751)Online publication date: 24-Aug-2015
  • Show More Cited By

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