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Automatic parallelization of simulink applications

Published: 24 April 2010 Publication History
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  • Abstract

    The parallelization of Simulink applications is currently a responsibility of the system designer and the superscalar execution of the processors. State-of-the-art Simulink compilers excel at producing reliable and production-quality embedded code, but fail to exploit the natural concurrency available in the programs and to effectively use modern multi-core architectures. The reason may be that many Simulink applications are replete with loop-carried dependencies that inhibit most parallel computing techniques and compiler transformations.
    In this paper, we introduce the concept of strands that allow the data dependencies to be broken while preserving the original semantics of the Simulink program. Our fully automatic compiler transformations create a concurrent representation of the program, and thread-level parallelism for multi-core systems is planned and orchestrated. To improve single processor performance, we also exploit fine grain (equation-level) parallelism by level-order scheduling inside each thread. Our strand transformation has been implemented as an automatic transformation in a proprietary compiler and with a realistic aeronautic model executed in two processors leads to an up to 1.98 times speedup over uniprocessor execution, while the existing manual parallelization method achieves a 1.75 times speedup.

    References

    [1]
    Mathworks, "Simulink." http://www.mathworks.com/products/simulink/.
    [2]
    T. Stavros, S. Christos, C. Paul, and C. Adrian, "Translating Discrete-time Simulink to Lustre," Trans. on Embedded Computing Sys., vol. 4, no. 4, pp. 779--818, 2005.
    [3]
    J. Dannenberg and C. Kleinhans, "The Coming Age of Collaboration in the Automotive Industry," Mercer Manage. J., vol. 18, pp. 88--94, 2004.
    [4]
    B. Hardung, T. Kolzow, and A. Kruger, "Reuse of Software in Distributed Embedded Automotive Systems," in EMSOFT '04, pp. 203--210, ACM, 2004.
    [5]
    dSPACE, "RTI-MP dSPACE. http://www.dspaceinc.com/ww/en/inc/home/products/sw/impsw/rtimpblo.cfm.
    [6]
    L. Brisolara, S.-i. Han, X. Guerin, L. Carro, R. Reis, S.-I. Chae, and A. Jerraya, "Reducing Fine-Grain Communication Overhead in Multithread Code Generation for Heterogeneous MPSoC," in SCOPES '07, pp. 81---89, ACM, 2007.
    [7]
    G. H. Mealy, "A Method for Synthesizing Sequential Circuits," Bell System Technical Journal, vol. 34, pp. 1045--1079, 1955.
    [8]
    Mathworks, "Simulink User's Guide." http://www.mathworks.com/access/helpdesk/help/toolbox/simulink/ug/bqchgnk.html.
    [9]
    T. Fossen and T. Perez, "Marine Systems Simulator (MSS)." http://www.marinecontrol.org/.
    [10]
    IBM, "BlueLink Compiler." http://domino.research.ibm.com/comm/research_projects.nsf/pages/bluelink.index.html}.
    [11]
    M. R. Garey and D. S. Johnson, Computers and Intractability: A guide to the Theory of NP-Completeness. W H Freeman & Co}, 1979.
    [12]
    N. Andersson and P. Fritzson, "Generating Parallel Code from Object Oriented Mathematical Models," in POPP '95, pp. 48--57, ACM, 1995.
    [13]
    H. Lundvall, K. Stavaaker, P. Fritzson, and C. Kessler, "Automatic Parallelization of Simulation Code for Equation-based Models with Software Pipelining and Measurements on Three Platforms," SIGARCH Comput. Archit. News, vol. 36, no. 5, pp. 46--55, 2008.
    [14]
    A. Canedo, "Leveraging Equation-Level Parallelism in Simulink Compilation," IBM Research Report RT0848, 2009.
    [15]
    S. P. Amarasinghe and M. S. Lam, "Communication Optimization and Code Generation for Distributed Memory Machines," in PLDI '93: Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, (New York, NY, USA), pp. 126--138, ACM, 1993.
    [16]
    A. Zhai, J. G. Steffan, C. B. Colohan, and T. C. Mowry, "Compiler and Hardware Support for Reducing the Synchronization of Speculative Threads," ACM Trans. Archit. Code Optim., vol. 5, no. 1, pp. 1--33, 2008.
    [17]
    J. Giacomoni, T. Moseley, and M. Vachharajani, "FastForward for Efficient Pipeline Parallelism," in PACT '07, p. 407, IEEE Computer Society, 2007.
    [18]
    U. of California, "SLUGS." http://slugsuav.soe.ucsc.edu/.
    [19]
    M. I. Lizarraga, V. Dobrokhodov, G. H. Elkaim, R. Curry, and I. Kaminer, "Simulink Based Hardware-in-the-Loop Simulator for Rapid Prototyping of UAV Control Algorithms," Americal Institute of Aeronautics and Astronautics, 2009.
    [20]
    D. Word, J. J. Zenor, R. Bednar, R. E. Crosbie, and N. G. Hingorani, "Multi-rate Real-time Simulation Techniques," in SCSC: Proc. of 2007 summer computer simulation conference, pp. 195--198, Society for Computer Simulation International, 2007.
    [21]
    A. Ohata, J. Kako, T. Shen, and K. Ito, "Introduction to the Benchmark Challenge on SICE Engine Start Control Problem," in Proc. of the 17th World Congress, pp. 1048--1053, The Intl. Federation of Automatic Control, 2008.
    [22]
    H. Hanselmann, U. Kiffmeier, L. Koster, M. Meyer, and A. Rukgauer, "Production Quality Code Generation from Simulink Block Diagrams," IEEE CACSD'99, pp. 213--218, 1999.
    [23]
    M. D. Natale and V. Pappalardo, "Buffer Optimization in Multitask Implementations of Simulink Models," ACM Trans. Embed. Comput. Syst., vol. 7, no. 3, pp. 1--32, 2008.
    [24]
    P. Aronsson, P. Fritzson, and F. M. Models, "Multiprocessor Scheduling of Simulation Code from Modelica Models," 2002.
    [25]
    INRIA, "Scicos: Block diagram modeler/simulator." http://www.scicos.org/.
    [26]
    R. Cytron, "Doacross: Beyond Vectorization for Multiprocessors," in ICPP, pp. 836--844, 1986.
    [27]
    G. Ottoni, R. Rangan, A. Stoler, and D. I. August, "Automatic thread extraction with decoupled software pipelining," in MICRO, pp. 105--118, 2005.
    [28]
    N. Vachharajani, R. Rangan, E. Raman, M. J. Bridges, G. Ottoni, and D. I. August, "Speculative Decoupled Software Pipelining," in PACT '07, pp. 49--59, IEEE Computer Society, 2007.

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    cover image ACM Conferences
    CGO '10: Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
    April 2010
    300 pages
    ISBN:9781605586359
    DOI:10.1145/1772954
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 24 April 2010

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    Author Tags

    1. automatic parallelization
    2. coarse grain dataflow
    3. compilers
    4. equation-level parallelism
    5. multi-core
    6. simulink
    7. strands

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    • (2017)Semi-automatic parallelization of simulations with model transformation techniquesProceedings of the Symposium on Model-driven Approaches for Simulation Engineering10.5555/3108244.3108246(1-12)Online publication date: 23-Apr-2017
    • (2016)Automatic Parallelization of Multirate Block Diagrams of Control Systems on Multicore PlatformsACM Transactions on Embedded Computing Systems10.1145/295005516:1(1-26)Online publication date: 13-Oct-2016
    • (2015)Software Pipeline–Based Partitioning Method with Trade-Off between Workload Balance and Communication OptimizationETRI Journal10.4218/etrij.15.0114.050237:3(562-572)Online publication date: 1-Jun-2015
    • (2015)Automatic Parallelization of Simulink Models for Multi-core ArchitecturesProceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and Systems10.1109/HPCC-CSS-ICESS.2015.232(964-971)Online publication date: 24-Aug-2015
    • (2015)Multigrain Parallelization for Model-Based Design Applications Using the OSCAR CompilerRevised Selected Papers of the 28th International Workshop on Languages and Compilers for Parallel Computing - Volume 951910.1007/978-3-319-29778-1_8(125-139)Online publication date: 9-Sep-2015
    • (2014)A parallelizing compiler for multicore systemsProceedings of the 17th International Workshop on Software and Compilers for Embedded Systems10.1145/2609248.2609254(138-141)Online publication date: 10-Jun-2014
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    • (2013)An Automatic Parallel-Stage Decoupled Software Pipelining Parallelization Algorithm Based on OpenMPProceedings of the 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2013.227(1825-1831)Online publication date: 16-Jul-2013
    • (2013)A Compile-Time Cost Model for Automatic OpenMP Decoupled Software Pipelining ParallelizationProceedings of the 2013 14th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing10.1109/SNPD.2013.8(253-260)Online publication date: 1-Jul-2013
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