research-article

Cost-aware three-dimensional (3D) many-core multiprocessor design

Authors:

Yuan XieAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 126 - 131

https://doi.org/10.1145/1837274.1837308

Published: 13 June 2010 Publication History

Abstract

The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor design has been shifting from multi-core to many-core, questions such as whether 3D integration should be adopted, and how to choose among various design options must be addressed at the early design stage. In order to guide the final design towards a cost-effective direction, system-level cost evaluation is one of the most critical issues to be considered. In this paper, we propose a 3D many-core multiprocessor cost model, which includes wafer, bonding, package, and cooling cost analysis. Using the proposed cost model, we evaluate the optimal partitioning strategies for 16-, 32- and 64-core multiprocessors from the cost point of view.

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Cited By

Qian CHuang LYu QWang ZChilders BKaeli DPericàs M(2018)CMHProceedings of the 15th ACM International Conference on Computing Frontiers10.1145/3203217.3203235(121-128)Online publication date: 8-May-2018
https://dl.acm.org/doi/10.1145/3203217.3203235
Mandora HPatel DDubey N(2018)Migration and Cooling Aware Approach for Virtual Machine Spreading in Data Centers2018 3rd International Conference for Convergence in Technology (I2CT)10.1109/I2CT.2018.8529739(1-6)Online publication date: Apr-2018
https://doi.org/10.1109/I2CT.2018.8529739
Zhao JZou QXie Y(2017)Overview of 3-D Architecture Design Opportunities and TechniquesIEEE Design & Test10.1109/MDAT.2015.246328234:4(60-68)Online publication date: Aug-2017
https://doi.org/10.1109/MDAT.2015.2463282
Show More Cited By

Index Terms

Cost-aware three-dimensional (3D) many-core multiprocessor design
1. Hardware
  1. Integrated circuits

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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National Science Foundation

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DAC '10

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Qian CHuang LYu QWang ZChilders BKaeli DPericàs M(2018)CMHProceedings of the 15th ACM International Conference on Computing Frontiers10.1145/3203217.3203235(121-128)Online publication date: 8-May-2018
https://dl.acm.org/doi/10.1145/3203217.3203235
Mandora HPatel DDubey N(2018)Migration and Cooling Aware Approach for Virtual Machine Spreading in Data Centers2018 3rd International Conference for Convergence in Technology (I2CT)10.1109/I2CT.2018.8529739(1-6)Online publication date: Apr-2018
https://doi.org/10.1109/I2CT.2018.8529739
Zhao JZou QXie Y(2017)Overview of 3-D Architecture Design Opportunities and TechniquesIEEE Design & Test10.1109/MDAT.2015.246328234:4(60-68)Online publication date: Aug-2017
https://doi.org/10.1109/MDAT.2015.2463282
Zhao JXu CZhang TXie Y(2016)BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile MemoriesJournal of Computer Science and Technology10.1007/s11390-016-1609-731:1(20-35)Online publication date: 8-Jan-2016
https://doi.org/10.1007/s11390-016-1609-7
Beece AMilojevic Dvan der Plas GAugur RSureddin MSingh JSenapati BBouche GAlapati RStephens JLin IRashed MYuan LKye JWoo YWehbi AHang PTon-That VKanagala VYu DGao SSamavedam S(2015)Quantitative Projections of the Cost Benefits of 3D IntegrationInternational Symposium on Microelectronics10.4071/isom-2015-TP212015:1(000035-000040)Online publication date: 3-Oct-2015
https://doi.org/10.4071/isom-2015-TP21
Demir YHardavellas NIvanov AMarculescu DPande PFlich JPattabiraman K(2015)ParkaProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786597(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2786597
Ying Wang Yin-He Han Lei Zhang Bin-Zhang Fu Cheng Liu Hua-Wei Li Xiaowei Li (2015)Economizing TSV Resources in 3-D Network-on-Chip DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231183523:3(493-506)Online publication date: Mar-2015
https://doi.org/10.1109/TVLSI.2014.2311835
Zou QZhan JFen Ge Poremba MXie Y(2014)Designing vertical bandwidth reconfigurable 3D NoCs for many core systems2014 International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2014.7152186(1-7)Online publication date: Dec-2014
https://doi.org/10.1109/3DIC.2014.7152186
Zou QPoremba MXie Y(2014)A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests2014 International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2014.7152176(1-7)Online publication date: Dec-2014
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Niu DXu CMuralimanohar NJouppi NXie YHenkel J(2013)Design of cross-point metal-oxide ReRAM emphasizing reliability and costProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561832(17-23)Online publication date: 18-Nov-2013
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