research-article

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Authors:

Lin Xie,

Azadeh Davoodi,

Kewal K. SalujaAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 274 - 279

https://doi.org/10.1145/1837274.1837344

Published: 13 June 2010 Publication History

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Abstract

We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as "failing segments" and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of non-failing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high "diagnosis resolution" in identifying failing segments, and in ranking them.

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Cited By

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(2018)QBF-Based Post-Silicon Debug of Speed-Paths Under Timing VariationsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.2858291(1-10)Online publication date: 2018
https://doi.org/10.1109/TCSI.2018.2858291
Garcia-Espinosa ELongoria-Gandara OGonzalez-Garcia EVeloz-Guerrero A(2018)Post-silicon validation based on synthetic test patterns for early detection of timing anomalies2018 IEEE 19th Latin-American Test Symposium (LATS)10.1109/LATW.2018.8347237(1-5)Online publication date: Mar-2018
https://doi.org/10.1109/LATW.2018.8347237
Somashekar ATragoudas S(2017)Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay MeasurementsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257184936:2(325-335)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2571849
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Index Terms

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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Division of Computing and Communication Foundations

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DAC '10

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EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

(2018)QBF-Based Post-Silicon Debug of Speed-Paths Under Timing VariationsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.2858291(1-10)Online publication date: 2018
https://doi.org/10.1109/TCSI.2018.2858291
Garcia-Espinosa ELongoria-Gandara OGonzalez-Garcia EVeloz-Guerrero A(2018)Post-silicon validation based on synthetic test patterns for early detection of timing anomalies2018 IEEE 19th Latin-American Test Symposium (LATS)10.1109/LATW.2018.8347237(1-5)Online publication date: Mar-2018
https://doi.org/10.1109/LATW.2018.8347237
Somashekar ATragoudas S(2017)Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay MeasurementsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257184936:2(325-335)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2571849
Kaiss DKalechstain JJobstmann B(2014)Post-silicon Timing Diagnosis Made Simple using Formal TechnologyProceedings of the 14th Conference on Formal Methods in Computer-Aided Design10.5555/2682923.2682949(131-138)Online publication date: 21-Oct-2014
https://dl.acm.org/doi/10.5555/2682923.2682949
Dehbashi MFey G(2014)SAT-based speedpath debugging using X traces2014 9th International Design and Test Symposium (IDT)10.1109/IDT.2014.7038595(100-105)Online publication date: Dec-2014
https://doi.org/10.1109/IDT.2014.7038595
Kaiss DKalechstain J(2014)Post-silicon timing diagnosis made simple using formal technology2014 Formal Methods in Computer-Aided Design (FMCAD)10.1109/FMCAD.2014.6987605(131-138)Online publication date: Oct-2014
https://doi.org/10.1109/FMCAD.2014.6987605
Dehbashi MFey G(2014)Sat-based speedpath debugging using waveforms2014 19th IEEE European Test Symposium (ETS)10.1109/ETS.2014.6847802(1-6)Online publication date: May-2014
https://doi.org/10.1109/ETS.2014.6847802
Aljubouri WSomashekar AHaniotakis TTragoudas S(2014)Diagnosis of segment delay defects with current sensing2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2014.6962101(122-127)Online publication date: Oct-2014
https://doi.org/10.1109/DFT.2014.6962101
Dehbashi MFey GDehbashi MFey G(2014)Online Debug for NoC-Based Multiprocessor SoCsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_9(133-157)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_9
Dehbashi MFey GDehbashi MFey G(2014)Efficient Automated Speedpath DebuggingDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_8(115-129)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_8
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