Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/1840845.1840875acmconferencesArticle/Chapter ViewAbstractPublication PagesislpedConference Proceedingsconference-collections
poster

Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives

Published: 18 August 2010 Publication History

Abstract

Application-specific instruction set processor (ASIP) has become a promising platform for embedded system design in the past decade. Traditional custom instruction synthesis flows for ASIPs mainly target performance improvement. Other design metrics are not addressed appropriately. In this paper, we show that the existing custom instruction exploration algorithms and cost estimation methods for performance improvement only are not suitable for other important design objectives, such as increasing energy efficiency and reducing area overhead. We propose a holistic ASIP design flow that can be adapted to optimize performance, energy consumption, or area. We formulate the design space exploration problem into an operation scheduling process. Different algorithms are employed to find the corresponding best custom instruction set efficiently.

References

[1]
Xilinx Inc. {http://www.xilinx.com}.
[2]
CPLEX LP solver {http://www.ilog.com/}.
[3]
SUIF and MachSUIF Compiler {http://tclab.kaist.ac.kr/~kcshin/reference.htm}.
[4]
CoWare Inc. {http://www.coware.com/}.
[5]
MiBench. {http://www.eecs.umich.edu/mibench/}.
[6]
SimpleScalar Portable Instruction Set Architecture (PISA). {http://www.simplescalar.com/}.
[7]
Target Compiler Technologies. {http://www.retarget.com/}.
[8]
K. Atasu and G. D. C. Ozturan. An integer linear programming approach for identifying instruction-set extensions. In Proc. Int. Conf. on Hardware-Software Codesign & System Synthesis, pages 172--177, Sept. 2005.
[9]
P. Biswas, N. Dutt, P. Ienne, and L. Pozzi. Introduction of architecturally visible storage in instruction set extensions. IEEE Trans. Computer-Aided Design of Integrated Circuits, 26(3):3423--3455, Mar. 2007.
[10]
P. Brisk, A. Kaplan, and M. Sarrafzadeh. Area-efficient instruction sets synthesis for reconfigurable system-on-chip designs. In Proc. Design Automation Conf., pages 395--400, 2004.
[11]
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. Int. Symp. Computer Architecture, pages 83--94, 2000.
[12]
N. Clark, J. Blome, M. Chu, S. Mahlke, S. Biles, and K. Flautner. An architecture framework for transparent instruction set customization in embedded processors. In Proc. Int. Symp. Computer Architecture, pages 272--283, 2005.
[13]
N. Clark, H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customization. In Proc. Int. Symp. Microarchitecture, pages 129--140, Dec. 2003.
[14]
J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. In ACM Proc. Int. Symp. on Field-Programmable Gate Arrays, pages 183--189, Feb. 2004.
[15]
C. C. de Souza, A. M. Lima, G. Araujo, and N. Moreano. The datapath merging problem in reconfigurable systems: complexity, dual bounds, and heuristic evaluation. ACM J. of Experimental Algorithms, 10:1--19, 2005.
[16]
Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha. A hybrid energy estimation technique for extensible processors. IEEE Trans. Computer-Aided Design of Integrated Circuits, 23(5):652--664, May. 2004.
[17]
R. E. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20(2):60--70, 2000.
[18]
D. Goodwin and D. Petkov. Automatic generation of application specific processors. In Int. Conf. Compilers, Architecture, and Synthesis for Embedded Systems, pages 137--147, Oct. 2003.
[19]
R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh. Instruction generation for hybrid reconfigurable systems. ACM Trans. Design Automation of Electronic Systems, 7(4):605--627, Oct. 2002.
[20]
J.-E. Lee, K. Y. Choi, and N. D. Dutt. Energy-efficient instruction set synthesis for application-specific processors. In Proc. Int. Symp. Low Power Electronics & Design, pages 330--333, 2003.
[21]
H. Lin and Y. Fei. Harnessing horizontal and vertical parallelism of programs to improve system overall efficiency. In Proc. Design Automation & Test Europe Conf., pages 748--763, Mar. 2008.
[22]
L. Pozzi, K. Atasu, and P. Ienne. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Computer-Aided Design of Integrated Circuits, 25(7):1209--1229. 2006.
[23]
R. Ravindran, M. Chu, and S. Mahlke. Compiler-managed partitioned data caches for low power. In Proc. of LCTES Conf., pages 237--247, 2007.
[24]
R. A. Ravindran. Hardware/software techniques for memory power optimizations in embedded processors. Doctoral Dissertation, Computer Science and Engineering, University of Michigan, 2007.
[25]
F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Custom-instruction synthesis for extensible processor platform. IEEE Trans. Computer-Aided Design of Integrated Circuits, 23(2):216--228, Feb. 2004.
[26]
M. Zuluaga and N. Topham. Resource sharing in custom instruction set extensions. In Proc. IEEE Symp. on Application Specific Processors, pages 7--13, June 2008.

Cited By

View all
  • (2019)RewardProfiler: A Reward Based Design Space Profiler on DVFS Enabled MPSoCs2019 6th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/ 2019 5th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom)10.1109/CSCloud/EdgeCom.2019.00028(210-220)Online publication date: Jun-2019
  • (2014)Custom instruction search for application specific instruction-set processor using guided simulated annealing2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS.2014.7032796(367-370)Online publication date: Nov-2014
  • (2014)Domain-specific application analysis for customized instruction identificationMicroprocessors and Microsystems10.1016/j.micpro.2014.06.00638:7(637-648)Online publication date: Oct-2014
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
August 2010
458 pages
ISBN:9781450301466
DOI:10.1145/1840845
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

  • IEEE CAS

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. asips
  2. multi-objective design

Qualifiers

  • Poster

Conference

ISLPED'10
Sponsor:

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 03 Oct 2024

Other Metrics

Citations

Cited By

View all
  • (2019)RewardProfiler: A Reward Based Design Space Profiler on DVFS Enabled MPSoCs2019 6th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/ 2019 5th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom)10.1109/CSCloud/EdgeCom.2019.00028(210-220)Online publication date: Jun-2019
  • (2014)Custom instruction search for application specific instruction-set processor using guided simulated annealing2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS.2014.7032796(367-370)Online publication date: Nov-2014
  • (2014)Domain-specific application analysis for customized instruction identificationMicroprocessors and Microsystems10.1016/j.micpro.2014.06.00638:7(637-648)Online publication date: Oct-2014
  • (2013)Energy-aware synthesis of application specific MPSoCs2013 IEEE 31st International Conference on Computer Design (ICCD)10.1109/ICCD.2013.6657026(62-69)Online publication date: Oct-2013

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media